1# 2# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7override BL2_AT_EL3 := 1 8override COLD_BOOT_SINGLE_CPU := 1 9override PROGRAMMABLE_RESET_ADDRESS := 1 10override USE_COHERENT_MEM := 1 11override ENABLE_SVE_FOR_NS := 0 12 13# Disabling ENABLE_PIE saves memory footprint a lot, but you need to adjust 14# UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses. 15override ENABLE_PIE := 1 16 17ALLOW_RO_XLAT_TABLES := 1 18 19ifeq ($(ALLOW_RO_XLAT_TABLES),1) 20BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 21BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 22endif 23 24# The dynamic xlat table is only used in BL2 25BL2_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 26 27# Cortex-A53 revision r0p4-51rel0 28# needed for LD20, unneeded for LD11, PXs3 (no ACE) 29ERRATA_A53_855873 := 1 30 31FIP_ALIGN := 512 32 33ifeq ($(NEED_BL32),yes) 34$(eval $(call add_define,UNIPHIER_LOAD_BL32)) 35endif 36 37# Libraries 38include lib/xlat_tables_v2/xlat_tables.mk 39 40PLAT_PATH := plat/socionext/uniphier 41PLAT_INCLUDES := -I$(PLAT_PATH)/include 42 43# common sources for BL2, BL31 (and BL32 if SPD=tspd) 44PLAT_BL_COMMON_SOURCES += plat/common/aarch64/crash_console_helpers.S \ 45 $(PLAT_PATH)/uniphier_console.S \ 46 $(PLAT_PATH)/uniphier_console_setup.c \ 47 $(PLAT_PATH)/uniphier_helpers.S \ 48 $(PLAT_PATH)/uniphier_soc_info.c \ 49 $(PLAT_PATH)/uniphier_xlat_setup.c \ 50 ${XLAT_TABLES_LIB_SRCS} 51 52BL2_SOURCES += common/desc_image_load.c \ 53 drivers/io/io_block.c \ 54 drivers/io/io_fip.c \ 55 drivers/io/io_memmap.c \ 56 drivers/io/io_storage.c \ 57 lib/cpus/aarch64/cortex_a53.S \ 58 lib/cpus/aarch64/cortex_a72.S \ 59 $(PLAT_PATH)/uniphier_bl2_setup.c \ 60 $(PLAT_PATH)/uniphier_boot_device.c \ 61 $(PLAT_PATH)/uniphier_emmc.c \ 62 $(PLAT_PATH)/uniphier_image_desc.c \ 63 $(PLAT_PATH)/uniphier_io_storage.c \ 64 $(PLAT_PATH)/uniphier_nand.c \ 65 $(PLAT_PATH)/uniphier_scp.c \ 66 $(PLAT_PATH)/uniphier_usb.c 67 68# Include GICv3 driver files 69include drivers/arm/gic/v3/gicv3.mk 70 71BL31_SOURCES += drivers/arm/cci/cci.c \ 72 ${GICV3_SOURCES} \ 73 lib/cpus/aarch64/cortex_a53.S \ 74 lib/cpus/aarch64/cortex_a72.S \ 75 plat/common/plat_gicv3.c \ 76 plat/common/plat_psci_common.c \ 77 $(PLAT_PATH)/uniphier_bl31_setup.c \ 78 $(PLAT_PATH)/uniphier_boot_device.c \ 79 $(PLAT_PATH)/uniphier_cci.c \ 80 $(PLAT_PATH)/uniphier_gicv3.c \ 81 $(PLAT_PATH)/uniphier_psci.c \ 82 $(PLAT_PATH)/uniphier_scp.c \ 83 $(PLAT_PATH)/uniphier_smp.S \ 84 $(PLAT_PATH)/uniphier_syscnt.c \ 85 $(PLAT_PATH)/uniphier_topology.c 86 87ifeq (${TRUSTED_BOARD_BOOT},1) 88 89include drivers/auth/mbedtls/mbedtls_crypto.mk 90include drivers/auth/mbedtls/mbedtls_x509.mk 91 92BL2_SOURCES += drivers/auth/auth_mod.c \ 93 drivers/auth/crypto_mod.c \ 94 drivers/auth/img_parser_mod.c \ 95 drivers/auth/tbbr/tbbr_cot.c \ 96 plat/common/tbbr/plat_tbbr.c \ 97 $(PLAT_PATH)/uniphier_rotpk.S \ 98 $(PLAT_PATH)/uniphier_tbbr.c 99 100ROT_KEY = $(BUILD_PLAT)/rot_key.pem 101ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin 102 103$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) 104$(BUILD_PLAT)/bl2/uniphier_rotpk.o: $(ROTPK_HASH) 105 106certificates: $(ROT_KEY) 107$(ROT_KEY): | $(BUILD_PLAT) 108 @echo " OPENSSL $@" 109 $(Q)openssl genrsa 2048 > $@ 2>/dev/null 110 111$(ROTPK_HASH): $(ROT_KEY) 112 @echo " OPENSSL $@" 113 $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ 114 openssl dgst -sha256 -binary > $@ 2>/dev/null 115 116endif 117 118ifeq (${FIP_GZIP},1) 119 120include lib/zlib/zlib.mk 121 122BL2_SOURCES += common/image_decompress.c \ 123 $(ZLIB_SOURCES) 124 125$(eval $(call add_define,UNIPHIER_DECOMPRESS_GZIP)) 126 127# compress all images loaded by BL2 128SCP_BL2_PRE_TOOL_FILTER := GZIP 129BL31_PRE_TOOL_FILTER := GZIP 130BL32_PRE_TOOL_FILTER := GZIP 131BL33_PRE_TOOL_FILTER := GZIP 132 133endif 134 135.PHONY: bl2_gzip 136bl2_gzip: $(BUILD_PLAT)/bl2.bin.gz 137%.gz: % 138 @echo " GZIP $@" 139 $(Q)gzip -n -f -9 $< --stdout > $@ 140