xref: /rk3399_ARM-atf/plat/socionext/uniphier/platform.mk (revision 3429c77ab09b69eef4ed752c2d641ed724e72110)
1#
2# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7override COLD_BOOT_SINGLE_CPU	:= 1
8override ENABLE_PLAT_COMPAT	:= 0
9override ERROR_DEPRECATED	:= 1
10override LOAD_IMAGE_V2		:= 1
11override USE_COHERENT_MEM	:= 1
12override USE_TBBR_DEFS		:= 1
13override ENABLE_SVE_FOR_NS	:= 0
14
15# Cortex-A53 revision r0p4-51rel0
16# needed for LD20, unneeded for LD11, PXs3 (no ACE)
17ERRATA_A53_855873		:= 1
18
19FIP_ALIGN			:= 512
20
21ifeq ($(NEED_BL32),yes)
22$(eval $(call add_define,UNIPHIER_LOAD_BL32))
23endif
24
25# Libraries
26include lib/xlat_tables_v2/xlat_tables.mk
27
28PLAT_PATH		:=	plat/socionext/uniphier
29PLAT_INCLUDES		:=	-I$(PLAT_PATH)/include
30
31# IO sources for BL1, BL2
32IO_SOURCES		:=	drivers/io/io_block.c			\
33				drivers/io/io_fip.c			\
34				drivers/io/io_memmap.c			\
35				drivers/io/io_storage.c			\
36				$(PLAT_PATH)/uniphier_boot_device.c	\
37				$(PLAT_PATH)/uniphier_emmc.c		\
38				$(PLAT_PATH)/uniphier_io_storage.c	\
39				$(PLAT_PATH)/uniphier_nand.c		\
40				$(PLAT_PATH)/uniphier_usb.c
41
42# common sources for BL1, BL2, BL31
43PLAT_BL_COMMON_SOURCES	+=	drivers/console/aarch64/console.S	\
44				$(PLAT_PATH)/uniphier_console.S		\
45				$(PLAT_PATH)/uniphier_helpers.S		\
46				$(PLAT_PATH)/uniphier_soc_info.c	\
47				$(PLAT_PATH)/uniphier_xlat_setup.c	\
48				${XLAT_TABLES_LIB_SRCS}
49
50BL1_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
51				lib/cpus/aarch64/cortex_a72.S		\
52				$(PLAT_PATH)/uniphier_bl1_helpers.S	\
53				$(PLAT_PATH)/uniphier_bl1_setup.c	\
54				$(IO_SOURCES)
55
56BL2_SOURCES		+=	common/desc_image_load.c		\
57				$(PLAT_PATH)/uniphier_bl2_setup.c	\
58				$(PLAT_PATH)/uniphier_image_desc.c	\
59				$(PLAT_PATH)/uniphier_scp.c		\
60				$(IO_SOURCES)
61
62BL31_SOURCES		+=	drivers/arm/cci/cci.c			\
63				drivers/arm/gic/common/gic_common.c	\
64				drivers/arm/gic/v3/gicv3_helpers.c	\
65				drivers/arm/gic/v3/gicv3_main.c		\
66				lib/cpus/aarch64/cortex_a53.S		\
67				lib/cpus/aarch64/cortex_a72.S		\
68				plat/common/plat_gicv3.c		\
69				plat/common/plat_psci_common.c		\
70				$(PLAT_PATH)/uniphier_bl31_setup.c	\
71				$(PLAT_PATH)/uniphier_cci.c		\
72				$(PLAT_PATH)/uniphier_gicv3.c		\
73				$(PLAT_PATH)/uniphier_psci.c		\
74				$(PLAT_PATH)/uniphier_scp.c		\
75				$(PLAT_PATH)/uniphier_smp.S		\
76				$(PLAT_PATH)/uniphier_syscnt.c		\
77				$(PLAT_PATH)/uniphier_topology.c
78
79ifeq (${TRUSTED_BOARD_BOOT},1)
80
81include drivers/auth/mbedtls/mbedtls_crypto.mk
82include drivers/auth/mbedtls/mbedtls_x509.mk
83
84PLAT_INCLUDES		+=	-Iinclude/common/tbbr
85
86TBB_SOURCES		:=	drivers/auth/auth_mod.c			\
87				drivers/auth/crypto_mod.c		\
88				drivers/auth/img_parser_mod.c		\
89				drivers/auth/tbbr/tbbr_cot.c		\
90				plat/common/tbbr/plat_tbbr.c		\
91				$(PLAT_PATH)/uniphier_rotpk.S		\
92				$(PLAT_PATH)/uniphier_tbbr.c
93
94BL1_SOURCES		+=	$(TBB_SOURCES)
95BL2_SOURCES		+=	$(TBB_SOURCES)
96
97ROT_KEY			= $(BUILD_PLAT)/rot_key.pem
98ROTPK_HASH		= $(BUILD_PLAT)/rotpk_sha256.bin
99
100$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
101$(BUILD_PLAT)/bl1/uniphier_rotpk.o: $(ROTPK_HASH)
102$(BUILD_PLAT)/bl2/uniphier_rotpk.o: $(ROTPK_HASH)
103
104certificates: $(ROT_KEY)
105$(ROT_KEY): | $(BUILD_PLAT)
106	@echo "  OPENSSL $@"
107	$(Q)openssl genrsa 2048 > $@ 2>/dev/null
108
109$(ROTPK_HASH): $(ROT_KEY)
110	@echo "  OPENSSL $@"
111	$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
112	openssl dgst -sha256 -binary > $@ 2>/dev/null
113
114endif
115
116.PHONY: bl1_gzip
117bl1_gzip: $(BUILD_PLAT)/bl1.bin.gzip
118%.gzip: %
119	@echo " GZIP     $@"
120	$(Q)(cat $< | gzip -n -f -9 > $@) || (rm -f $@ || false)
121