1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #define PLATFORM_STACK_SIZE 0x1000 15 16 #define CACHE_WRITEBACK_SHIFT 6 17 #define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT)) 18 19 /* topology */ 20 #define UNIPHIER_MAX_CPUS_PER_CLUSTER 4 21 #define UNIPHIER_CLUSTER_COUNT 2 22 23 #define PLATFORM_CORE_COUNT \ 24 ((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT)) 25 26 #define PLAT_MAX_PWR_LVL U(1) 27 28 #define PLAT_MAX_OFF_STATE U(2) 29 #define PLAT_MAX_RET_STATE U(1) 30 31 #define BL2_BASE ULL(0x80000000) 32 #define BL2_LIMIT ULL(0x80080000) 33 34 /* 0x80080000-0x81000000: reserved for DSP */ 35 36 #define UNIPHIER_SEC_DRAM_BASE 0x81000000ULL 37 #define UNIPHIER_SEC_DRAM_LIMIT 0x82000000ULL 38 #define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \ 39 (UNIPHIER_SEC_DRAM_BASE)) 40 41 #define BL31_BASE ULL(0x81000000) 42 #define BL31_LIMIT ULL(0x81080000) 43 44 #define BL32_BASE ULL(0x81080000) 45 #define BL32_LIMIT ULL(0x81180000) 46 47 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 48 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 49 50 #define PLAT_XLAT_TABLES_DYNAMIC 1 51 #define MAX_XLAT_TABLES 7 52 #define MAX_MMAP_REGIONS 7 53 54 #define MAX_IO_HANDLES 2 55 #define MAX_IO_DEVICES 2 56 #define MAX_IO_BLOCK_DEVICES U(1) 57 58 #define TSP_SEC_MEM_BASE (BL32_BASE) 59 #define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE)) 60 #define TSP_IRQ_SEC_PHY_TIMER 29 61 62 #endif /* PLATFORM_DEF_H */ 63