1*d8e919c7SMasahiro Yamada /* 2*d8e919c7SMasahiro Yamada * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*d8e919c7SMasahiro Yamada * 4*d8e919c7SMasahiro Yamada * SPDX-License-Identifier: BSD-3-Clause 5*d8e919c7SMasahiro Yamada */ 6*d8e919c7SMasahiro Yamada 7*d8e919c7SMasahiro Yamada #ifndef __PLATFORM_DEF_H__ 8*d8e919c7SMasahiro Yamada #define __PLATFORM_DEF_H__ 9*d8e919c7SMasahiro Yamada 10*d8e919c7SMasahiro Yamada #include <common_def.h> 11*d8e919c7SMasahiro Yamada #include <tbbr/tbbr_img_def.h> 12*d8e919c7SMasahiro Yamada 13*d8e919c7SMasahiro Yamada #define PLATFORM_STACK_SIZE 0x1000 14*d8e919c7SMasahiro Yamada 15*d8e919c7SMasahiro Yamada #define CACHE_WRITEBACK_SHIFT 6 16*d8e919c7SMasahiro Yamada #define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT)) 17*d8e919c7SMasahiro Yamada 18*d8e919c7SMasahiro Yamada /* topology */ 19*d8e919c7SMasahiro Yamada #define UNIPHIER_MAX_CPUS_PER_CLUSTER 4 20*d8e919c7SMasahiro Yamada #define UNIPHIER_CLUSTER_COUNT 2 21*d8e919c7SMasahiro Yamada 22*d8e919c7SMasahiro Yamada #define PLATFORM_CORE_COUNT \ 23*d8e919c7SMasahiro Yamada ((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT)) 24*d8e919c7SMasahiro Yamada 25*d8e919c7SMasahiro Yamada #define PLAT_MAX_PWR_LVL 1 26*d8e919c7SMasahiro Yamada 27*d8e919c7SMasahiro Yamada #define PLAT_MAX_OFF_STATE 2 28*d8e919c7SMasahiro Yamada #define PLAT_MAX_RET_STATE 1 29*d8e919c7SMasahiro Yamada 30*d8e919c7SMasahiro Yamada #define UNIPHIER_SEC_DRAM_BASE 0x81000000 31*d8e919c7SMasahiro Yamada #define UNIPHIER_SEC_DRAM_LIMIT 0x82000000 32*d8e919c7SMasahiro Yamada #define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \ 33*d8e919c7SMasahiro Yamada (UNIPHIER_SEC_DRAM_BASE)) 34*d8e919c7SMasahiro Yamada 35*d8e919c7SMasahiro Yamada #define BL1_RO_BASE 0x80000000 36*d8e919c7SMasahiro Yamada #define BL1_RO_LIMIT 0x80018000 37*d8e919c7SMasahiro Yamada #define BL1_RW_LIMIT (UNIPHIER_SEC_DRAM_LIMIT) 38*d8e919c7SMasahiro Yamada #define BL1_RW_BASE ((BL1_RW_LIMIT) - 0x00040000) 39*d8e919c7SMasahiro Yamada 40*d8e919c7SMasahiro Yamada #define BL2_LIMIT (BL1_RW_BASE) 41*d8e919c7SMasahiro Yamada #define BL2_BASE ((BL2_LIMIT) - 0x00040000) 42*d8e919c7SMasahiro Yamada 43*d8e919c7SMasahiro Yamada #define BL31_BASE (UNIPHIER_SEC_DRAM_BASE) 44*d8e919c7SMasahiro Yamada #define BL31_LIMIT ((BL31_BASE) + 0x00080000) 45*d8e919c7SMasahiro Yamada 46*d8e919c7SMasahiro Yamada #define BL32_BASE (BL31_LIMIT) 47*d8e919c7SMasahiro Yamada #define BL32_LIMIT (UNIPHIER_SEC_DRAM_LIMIT) 48*d8e919c7SMasahiro Yamada 49*d8e919c7SMasahiro Yamada #define UNIPHIER_BLOCK_BUF_SIZE 0x00400000 50*d8e919c7SMasahiro Yamada #define UNIPHIER_BLOCK_BUF_BASE ((BL2_LIMIT) - \ 51*d8e919c7SMasahiro Yamada (UNIPHIER_BLOCK_BUF_SIZE)) 52*d8e919c7SMasahiro Yamada 53*d8e919c7SMasahiro Yamada #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 54*d8e919c7SMasahiro Yamada #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 55*d8e919c7SMasahiro Yamada 56*d8e919c7SMasahiro Yamada #define PLAT_XLAT_TABLES_DYNAMIC 1 57*d8e919c7SMasahiro Yamada #define MAX_XLAT_TABLES 7 58*d8e919c7SMasahiro Yamada #define MAX_MMAP_REGIONS 6 59*d8e919c7SMasahiro Yamada 60*d8e919c7SMasahiro Yamada #define MAX_IO_HANDLES 2 61*d8e919c7SMasahiro Yamada #define MAX_IO_DEVICES 2 62*d8e919c7SMasahiro Yamada #define MAX_IO_BLOCK_DEVICES 1 63*d8e919c7SMasahiro Yamada 64*d8e919c7SMasahiro Yamada #endif /* __PLATFORM_DEF_H__ */ 65