1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <common/debug.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 12 #define SQ_REG_REGION_BASE 0x20000000ULL 13 #define SQ_REG_REGION_SIZE 0x60000000ULL 14 15 void sq_mmap_setup(uintptr_t total_base, size_t total_size, 16 const struct mmap_region *mmap) 17 { 18 VERBOSE("Trusted RAM seen by this BL image: %p - %p\n", 19 (void *)total_base, (void *)(total_base + total_size)); 20 mmap_add_region(total_base, total_base, 21 total_size, 22 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 23 24 /* remap the code section */ 25 VERBOSE("Code region: %p - %p\n", 26 (void *)BL_CODE_BASE, (void *)BL_CODE_END); 27 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 28 round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE, 29 MT_NON_CACHEABLE | MT_RO | MT_SECURE); 30 31 /* Re-map the read-only data section */ 32 VERBOSE("Read-only data region: %p - %p\n", 33 (void *)BL_RO_DATA_BASE, (void *)BL_RO_DATA_END); 34 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 35 round_up(BL_RO_DATA_END, PAGE_SIZE) - BL_RO_DATA_BASE, 36 (MT_NON_CACHEABLE | MT_RO | MT_EXECUTE_NEVER | 37 MT_SECURE)); 38 39 /* remap the coherent memory region */ 40 VERBOSE("Coherent region: %p - %p\n", 41 (void *)BL_COHERENT_RAM_BASE, (void *)BL_COHERENT_RAM_END); 42 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 43 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 44 MT_DEVICE | MT_RW | MT_SECURE); 45 46 /* register region */ 47 mmap_add_region(SQ_REG_REGION_BASE, SQ_REG_REGION_BASE, 48 SQ_REG_REGION_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE); 50 51 /* additional regions if needed */ 52 if (mmap) 53 mmap_add(mmap); 54 55 init_xlat_tables(); 56 } 57