1*007a7a33SSumit Garg /* 2*007a7a33SSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*007a7a33SSumit Garg * 4*007a7a33SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5*007a7a33SSumit Garg */ 6*007a7a33SSumit Garg 7*007a7a33SSumit Garg #include <arch.h> 8*007a7a33SSumit Garg #include <sq_common.h> 9*007a7a33SSumit Garg #include <platform_def.h> 10*007a7a33SSumit Garg 11*007a7a33SSumit Garg unsigned char sq_pd_tree_desc[PLAT_CLUSTER_COUNT + 1]; 12*007a7a33SSumit Garg 13*007a7a33SSumit Garg int plat_core_pos_by_mpidr(u_register_t mpidr) 14*007a7a33SSumit Garg { 15*007a7a33SSumit Garg unsigned int cluster_id, cpu_id; 16*007a7a33SSumit Garg 17*007a7a33SSumit Garg cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 18*007a7a33SSumit Garg if (cluster_id >= PLAT_CLUSTER_COUNT) 19*007a7a33SSumit Garg return -1; 20*007a7a33SSumit Garg 21*007a7a33SSumit Garg cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 22*007a7a33SSumit Garg if (cpu_id >= PLAT_MAX_CORES_PER_CLUSTER) 23*007a7a33SSumit Garg return -1; 24*007a7a33SSumit Garg 25*007a7a33SSumit Garg return sq_calc_core_pos(mpidr); 26*007a7a33SSumit Garg } 27*007a7a33SSumit Garg 28*007a7a33SSumit Garg const unsigned char *plat_get_power_domain_tree_desc(void) 29*007a7a33SSumit Garg { 30*007a7a33SSumit Garg int i; 31*007a7a33SSumit Garg 32*007a7a33SSumit Garg sq_pd_tree_desc[0] = PLAT_CLUSTER_COUNT; 33*007a7a33SSumit Garg 34*007a7a33SSumit Garg for (i = 0; i < PLAT_CLUSTER_COUNT; i++) 35*007a7a33SSumit Garg sq_pd_tree_desc[i + 1] = PLAT_MAX_CORES_PER_CLUSTER; 36*007a7a33SSumit Garg 37*007a7a33SSumit Garg return sq_pd_tree_desc; 38*007a7a33SSumit Garg } 39