xref: /rk3399_ARM-atf/plat/socionext/synquacer/sq_spm.c (revision 434454a2710eea3f49ebfca951019d7b6c783fb5)
1*434454a2SArd Biesheuvel /*
2*434454a2SArd Biesheuvel  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*434454a2SArd Biesheuvel  *
4*434454a2SArd Biesheuvel  * SPDX-License-Identifier: BSD-3-Clause
5*434454a2SArd Biesheuvel  */
6*434454a2SArd Biesheuvel 
7*434454a2SArd Biesheuvel #include <assert.h>
8*434454a2SArd Biesheuvel 
9*434454a2SArd Biesheuvel #include <platform_def.h>
10*434454a2SArd Biesheuvel 
11*434454a2SArd Biesheuvel #include <bl31/ehf.h>
12*434454a2SArd Biesheuvel #include <lib/xlat_tables/xlat_tables_v2.h>
13*434454a2SArd Biesheuvel #include <services/secure_partition.h>
14*434454a2SArd Biesheuvel 
15*434454a2SArd Biesheuvel static const mmap_region_t plat_arm_secure_partition_mmap[] = {
16*434454a2SArd Biesheuvel 	PLAT_SQ_FLASH_MMAP,
17*434454a2SArd Biesheuvel 	PLAT_SQ_UART1_MMAP,
18*434454a2SArd Biesheuvel 	PLAT_SQ_PERIPH_MMAP,
19*434454a2SArd Biesheuvel 	PLAT_SQ_SP_IMAGE_MMAP,
20*434454a2SArd Biesheuvel 	PLAT_SP_IMAGE_NS_BUF_MMAP,
21*434454a2SArd Biesheuvel 	PLAT_SQ_SP_IMAGE_RW_MMAP,
22*434454a2SArd Biesheuvel 	PLAT_SPM_SPM_BUF_EL0_MMAP,
23*434454a2SArd Biesheuvel 	{0}
24*434454a2SArd Biesheuvel };
25*434454a2SArd Biesheuvel 
26*434454a2SArd Biesheuvel /*
27*434454a2SArd Biesheuvel  * Boot information passed to a secure partition during initialisation. Linear
28*434454a2SArd Biesheuvel  * indices in MP information will be filled at runtime.
29*434454a2SArd Biesheuvel  */
30*434454a2SArd Biesheuvel static secure_partition_mp_info_t sp_mp_info[] = {
31*434454a2SArd Biesheuvel 	{0x80000000, 0}, {0x80000001, 0}, {0x80000100, 0}, {0x80000101, 0},
32*434454a2SArd Biesheuvel 	{0x80000200, 0}, {0x80000201, 0}, {0x80000300, 0}, {0x80000301, 0},
33*434454a2SArd Biesheuvel 	{0x80000400, 0}, {0x80000401, 0}, {0x80000500, 0}, {0x80000501, 0},
34*434454a2SArd Biesheuvel 	{0x80000600, 0}, {0x80000601, 0}, {0x80000700, 0}, {0x80000701, 0},
35*434454a2SArd Biesheuvel 	{0x80000800, 0}, {0x80000801, 0}, {0x80000900, 0}, {0x80000901, 0},
36*434454a2SArd Biesheuvel 	{0x80000a00, 0}, {0x80000a01, 0}, {0x80000b00, 0}, {0x80000b01, 0},
37*434454a2SArd Biesheuvel };
38*434454a2SArd Biesheuvel 
39*434454a2SArd Biesheuvel const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
40*434454a2SArd Biesheuvel 	.h.type			= PARAM_SP_IMAGE_BOOT_INFO,
41*434454a2SArd Biesheuvel 	.h.version		= VERSION_1,
42*434454a2SArd Biesheuvel 	.h.size			= sizeof(secure_partition_boot_info_t),
43*434454a2SArd Biesheuvel 	.h.attr			= 0,
44*434454a2SArd Biesheuvel 	.sp_mem_base		= BL32_BASE,
45*434454a2SArd Biesheuvel 	.sp_mem_limit		= BL32_LIMIT,
46*434454a2SArd Biesheuvel 	.sp_image_base		= BL32_BASE,
47*434454a2SArd Biesheuvel 	.sp_stack_base		= PLAT_SP_IMAGE_STACK_BASE,
48*434454a2SArd Biesheuvel 	.sp_heap_base		= PLAT_SQ_SP_HEAP_BASE,
49*434454a2SArd Biesheuvel 	.sp_ns_comm_buf_base	= PLAT_SP_IMAGE_NS_BUF_BASE,
50*434454a2SArd Biesheuvel 	.sp_shared_buf_base	= PLAT_SPM_BUF_BASE,
51*434454a2SArd Biesheuvel 	.sp_image_size		= PLAT_SQ_SP_IMAGE_SIZE,
52*434454a2SArd Biesheuvel 	.sp_pcpu_stack_size	= PLAT_SP_IMAGE_STACK_PCPU_SIZE,
53*434454a2SArd Biesheuvel 	.sp_heap_size		= PLAT_SQ_SP_HEAP_SIZE,
54*434454a2SArd Biesheuvel 	.sp_ns_comm_buf_size	= PLAT_SP_IMAGE_NS_BUF_SIZE,
55*434454a2SArd Biesheuvel 	.sp_shared_buf_size	= PLAT_SPM_BUF_SIZE,
56*434454a2SArd Biesheuvel 	.num_sp_mem_regions	= PLAT_SP_IMAGE_NUM_MEM_REGIONS,
57*434454a2SArd Biesheuvel 	.num_cpus		= PLATFORM_CORE_COUNT,
58*434454a2SArd Biesheuvel 	.mp_info		= sp_mp_info,
59*434454a2SArd Biesheuvel };
60*434454a2SArd Biesheuvel 
61*434454a2SArd Biesheuvel const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
62*434454a2SArd Biesheuvel {
63*434454a2SArd Biesheuvel 	return plat_arm_secure_partition_mmap;
64*434454a2SArd Biesheuvel }
65*434454a2SArd Biesheuvel 
66*434454a2SArd Biesheuvel const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
67*434454a2SArd Biesheuvel 		void *cookie)
68*434454a2SArd Biesheuvel {
69*434454a2SArd Biesheuvel 	return &plat_arm_secure_partition_boot_info;
70*434454a2SArd Biesheuvel }
71*434454a2SArd Biesheuvel 
72*434454a2SArd Biesheuvel static ehf_pri_desc_t sq_exceptions[] = {
73*434454a2SArd Biesheuvel 	EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
74*434454a2SArd Biesheuvel };
75*434454a2SArd Biesheuvel EHF_REGISTER_PRIORITIES(sq_exceptions, ARRAY_SIZE(sq_exceptions), PLAT_PRI_BITS);
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