1*48ab3904SJassi Brar /* 2*48ab3904SJassi Brar * Copyright (c) 2022, Socionext Inc. All rights reserved. 3*48ab3904SJassi Brar * 4*48ab3904SJassi Brar * SPDX-License-Identifier: BSD-3-Clause 5*48ab3904SJassi Brar */ 6*48ab3904SJassi Brar 7*48ab3904SJassi Brar #include <assert.h> 8*48ab3904SJassi Brar 9*48ab3904SJassi Brar #include <arch.h> 10*48ab3904SJassi Brar #include <common/desc_image_load.h> 11*48ab3904SJassi Brar 12*48ab3904SJassi Brar #include <platform_def.h> 13*48ab3904SJassi Brar 14*48ab3904SJassi Brar static struct bl_mem_params_node sq_image_descs[] = { 15*48ab3904SJassi Brar { 16*48ab3904SJassi Brar .image_id = BL31_IMAGE_ID, 17*48ab3904SJassi Brar 18*48ab3904SJassi Brar SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, 19*48ab3904SJassi Brar VERSION_2, image_info_t, 0), 20*48ab3904SJassi Brar .image_info.image_base = BL31_BASE, 21*48ab3904SJassi Brar .image_info.image_max_size = BL31_SIZE, 22*48ab3904SJassi Brar 23*48ab3904SJassi Brar SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, 24*48ab3904SJassi Brar VERSION_2, entry_point_info_t, 25*48ab3904SJassi Brar SECURE | EXECUTABLE | EP_FIRST_EXE), 26*48ab3904SJassi Brar .ep_info.pc = BL31_BASE, 27*48ab3904SJassi Brar .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 28*48ab3904SJassi Brar DISABLE_ALL_EXCEPTIONS), 29*48ab3904SJassi Brar 30*48ab3904SJassi Brar .next_handoff_image_id = BL32_IMAGE_ID, 31*48ab3904SJassi Brar }, 32*48ab3904SJassi Brar { 33*48ab3904SJassi Brar .image_id = BL32_IMAGE_ID, 34*48ab3904SJassi Brar 35*48ab3904SJassi Brar SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, 36*48ab3904SJassi Brar VERSION_2, image_info_t, 0), 37*48ab3904SJassi Brar .image_info.image_base = BL32_BASE, 38*48ab3904SJassi Brar .image_info.image_max_size = BL32_SIZE, 39*48ab3904SJassi Brar 40*48ab3904SJassi Brar SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, 41*48ab3904SJassi Brar VERSION_2, entry_point_info_t, 42*48ab3904SJassi Brar SECURE | EXECUTABLE), 43*48ab3904SJassi Brar .ep_info.pc = BL32_BASE, 44*48ab3904SJassi Brar .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 45*48ab3904SJassi Brar DISABLE_ALL_EXCEPTIONS), 46*48ab3904SJassi Brar 47*48ab3904SJassi Brar .next_handoff_image_id = BL33_IMAGE_ID, 48*48ab3904SJassi Brar }, 49*48ab3904SJassi Brar { 50*48ab3904SJassi Brar .image_id = BL33_IMAGE_ID, 51*48ab3904SJassi Brar 52*48ab3904SJassi Brar SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, 53*48ab3904SJassi Brar VERSION_2, image_info_t, 0), 54*48ab3904SJassi Brar .image_info.image_base = PLAT_SQ_BL33_BASE, 55*48ab3904SJassi Brar .image_info.image_max_size = PLAT_SQ_BL33_SIZE, 56*48ab3904SJassi Brar 57*48ab3904SJassi Brar SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, 58*48ab3904SJassi Brar VERSION_2, entry_point_info_t, 59*48ab3904SJassi Brar NON_SECURE | EXECUTABLE), 60*48ab3904SJassi Brar .ep_info.pc = PLAT_SQ_BL33_BASE, 61*48ab3904SJassi Brar .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 62*48ab3904SJassi Brar DISABLE_ALL_EXCEPTIONS), 63*48ab3904SJassi Brar 64*48ab3904SJassi Brar .next_handoff_image_id = INVALID_IMAGE_ID, 65*48ab3904SJassi Brar }, 66*48ab3904SJassi Brar }; 67*48ab3904SJassi Brar REGISTER_BL_IMAGE_DESCS(sq_image_descs) 68*48ab3904SJassi Brar 69*48ab3904SJassi Brar struct image_info *sq_get_image_info(unsigned int image_id) 70*48ab3904SJassi Brar { 71*48ab3904SJassi Brar struct bl_mem_params_node *desc; 72*48ab3904SJassi Brar 73*48ab3904SJassi Brar desc = get_bl_mem_params_node(image_id); 74*48ab3904SJassi Brar assert(desc); 75*48ab3904SJassi Brar return &desc->image_info; 76*48ab3904SJassi Brar } 77