1/* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <platform_def.h> 11 12 .global sq_calc_core_pos 13 .global plat_my_core_pos 14 .global platform_mem_init 15 .global plat_is_my_cpu_primary 16 .global plat_secondary_cold_boot_setup 17 18/* 19 * unsigned int sq_calc_core_pos(u_register_t mpidr) 20 * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 21 */ 22func sq_calc_core_pos 23 and x1, x0, #MPIDR_CPU_MASK 24 and x0, x0, #MPIDR_CLUSTER_MASK 25 add x0, x1, x0, lsr #7 26 ret 27endfunc sq_calc_core_pos 28 29func plat_my_core_pos 30 mrs x0, mpidr_el1 31 b sq_calc_core_pos 32endfunc plat_my_core_pos 33 34func platform_mem_init 35 ret 36endfunc platform_mem_init 37 38/* 39 * Secondary CPUs are placed in a holding pen, waiting for their mailbox 40 * to be populated. Note that all CPUs share the same mailbox ; therefore, 41 * populating it will release all CPUs from their holding pen. If 42 * finer-grained control is needed then this should be handled in the 43 * code that secondary CPUs jump to. 44 */ 45func plat_secondary_cold_boot_setup 46 ldr x0, sq_sec_entrypoint 47 48 /* Wait until the mailbox gets populated */ 49poll_mailbox: 50 cbz x0, 1f 51 br x0 521: 53 wfe 54 b poll_mailbox 55endfunc plat_secondary_cold_boot_setup 56 57/* 58 * Find out whether the current cpu is the primary 59 * cpu (applicable only after a cold boot) 60 */ 61func plat_is_my_cpu_primary 62 mov x9, x30 63 bl plat_my_core_pos 64 ldr x1, =SQ_BOOT_CFG_ADDR 65 ldr x1, [x1] 66 ubfx x1, x1, #PLAT_SQ_PRIMARY_CPU_SHIFT, \ 67 #PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 68 cmp x0, x1 69 cset w0, eq 70 ret x9 71endfunc plat_is_my_cpu_primary 72