1*85427debSSumit Garg/* 2*85427debSSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*85427debSSumit Garg * 4*85427debSSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5*85427debSSumit Garg */ 6*85427debSSumit Garg 7*85427debSSumit Garg#include <arch.h> 8*85427debSSumit Garg#include <asm_macros.S> 9*85427debSSumit Garg#include <assert_macros.S> 10*85427debSSumit Garg#include <platform_def.h> 11*85427debSSumit Garg 12*85427debSSumit Garg .global sq_calc_core_pos 13*85427debSSumit Garg .global plat_my_core_pos 14*85427debSSumit Garg .global platform_mem_init 15*85427debSSumit Garg .global plat_is_my_cpu_primary 16*85427debSSumit Garg .global plat_secondary_cold_boot_setup 17*85427debSSumit Garg 18*85427debSSumit Garg/* 19*85427debSSumit Garg * unsigned int sq_calc_core_pos(u_register_t mpidr) 20*85427debSSumit Garg * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 21*85427debSSumit Garg */ 22*85427debSSumit Gargfunc sq_calc_core_pos 23*85427debSSumit Garg and x1, x0, #MPIDR_CPU_MASK 24*85427debSSumit Garg and x0, x0, #MPIDR_CLUSTER_MASK 25*85427debSSumit Garg add x0, x1, x0, lsr #7 26*85427debSSumit Garg ret 27*85427debSSumit Gargendfunc sq_calc_core_pos 28*85427debSSumit Garg 29*85427debSSumit Gargfunc plat_my_core_pos 30*85427debSSumit Garg mrs x0, mpidr_el1 31*85427debSSumit Garg b sq_calc_core_pos 32*85427debSSumit Gargendfunc plat_my_core_pos 33*85427debSSumit Garg 34*85427debSSumit Gargfunc platform_mem_init 35*85427debSSumit Garg ret 36*85427debSSumit Gargendfunc platform_mem_init 37*85427debSSumit Garg 38*85427debSSumit Garg/* 39*85427debSSumit Garg * Secondary CPUs are placed in a holding pen, waiting for their mailbox 40*85427debSSumit Garg * to be populated. Note that all CPUs share the same mailbox ; therefore, 41*85427debSSumit Garg * populating it will release all CPUs from their holding pen. If 42*85427debSSumit Garg * finer-grained control is needed then this should be handled in the 43*85427debSSumit Garg * code that secondary CPUs jump to. 44*85427debSSumit Garg */ 45*85427debSSumit Gargfunc plat_secondary_cold_boot_setup 46*85427debSSumit Garg ldr x0, sq_sec_entrypoint 47*85427debSSumit Garg 48*85427debSSumit Garg /* Wait until the mailbox gets populated */ 49*85427debSSumit Gargpoll_mailbox: 50*85427debSSumit Garg cbz x0, 1f 51*85427debSSumit Garg br x0 52*85427debSSumit Garg1: 53*85427debSSumit Garg wfe 54*85427debSSumit Garg b poll_mailbox 55*85427debSSumit Gargendfunc plat_secondary_cold_boot_setup 56*85427debSSumit Garg 57*85427debSSumit Garg/* 58*85427debSSumit Garg * Find out whether the current cpu is the primary 59*85427debSSumit Garg * cpu (applicable only after a cold boot) 60*85427debSSumit Garg */ 61*85427debSSumit Gargfunc plat_is_my_cpu_primary 62*85427debSSumit Garg mov x9, x30 63*85427debSSumit Garg bl plat_my_core_pos 64*85427debSSumit Garg ldr x1, =SQ_BOOT_CFG_ADDR 65*85427debSSumit Garg ldr x1, [x1] 66*85427debSSumit Garg ubfx x1, x1, #PLAT_SQ_PRIMARY_CPU_SHIFT, \ 67*85427debSSumit Garg #PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 68*85427debSSumit Garg cmp x0, x1 69*85427debSSumit Garg cset w0, eq 70*85427debSSumit Garg ret x9 71*85427debSSumit Gargendfunc plat_is_my_cpu_primary 72