185427debSSumit Garg/* 2*48ab3904SJassi Brar * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 385427debSSumit Garg * 485427debSSumit Garg * SPDX-License-Identifier: BSD-3-Clause 585427debSSumit Garg */ 685427debSSumit Garg 785427debSSumit Garg#include <arch.h> 885427debSSumit Garg#include <asm_macros.S> 985427debSSumit Garg#include <assert_macros.S> 1085427debSSumit Garg#include <platform_def.h> 1185427debSSumit Garg 1285427debSSumit Garg .global sq_calc_core_pos 1385427debSSumit Garg .global plat_my_core_pos 1485427debSSumit Garg .global platform_mem_init 1585427debSSumit Garg .global plat_is_my_cpu_primary 1685427debSSumit Garg .global plat_secondary_cold_boot_setup 1767b40070SSumit Garg .global plat_crash_console_init 1867b40070SSumit Garg .global plat_crash_console_putc 1967b40070SSumit Garg .global plat_crash_console_flush 2085427debSSumit Garg 2185427debSSumit Garg/* 2285427debSSumit Garg * unsigned int sq_calc_core_pos(u_register_t mpidr) 2385427debSSumit Garg * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 2485427debSSumit Garg */ 2585427debSSumit Gargfunc sq_calc_core_pos 2685427debSSumit Garg and x1, x0, #MPIDR_CPU_MASK 2785427debSSumit Garg and x0, x0, #MPIDR_CLUSTER_MASK 2885427debSSumit Garg add x0, x1, x0, lsr #7 2985427debSSumit Garg ret 3085427debSSumit Gargendfunc sq_calc_core_pos 3185427debSSumit Garg 3285427debSSumit Gargfunc plat_my_core_pos 3385427debSSumit Garg mrs x0, mpidr_el1 3485427debSSumit Garg b sq_calc_core_pos 3585427debSSumit Gargendfunc plat_my_core_pos 3685427debSSumit Garg 3785427debSSumit Gargfunc platform_mem_init 3885427debSSumit Garg ret 3985427debSSumit Gargendfunc platform_mem_init 4085427debSSumit Garg 4185427debSSumit Garg/* 4285427debSSumit Garg * Secondary CPUs are placed in a holding pen, waiting for their mailbox 4385427debSSumit Garg * to be populated. Note that all CPUs share the same mailbox ; therefore, 4485427debSSumit Garg * populating it will release all CPUs from their holding pen. If 4585427debSSumit Garg * finer-grained control is needed then this should be handled in the 4685427debSSumit Garg * code that secondary CPUs jump to. 4785427debSSumit Garg */ 4885427debSSumit Gargfunc plat_secondary_cold_boot_setup 49*48ab3904SJassi Brar#if !RESET_TO_BL31 50*48ab3904SJassi Brar mov_imm x0, BL2_MAILBOX_BASE 51*48ab3904SJassi Brar ldr x0, [x0] 52*48ab3904SJassi Brar#else 5385427debSSumit Garg ldr x0, sq_sec_entrypoint 54*48ab3904SJassi Brar#endif 5585427debSSumit Garg 5685427debSSumit Garg /* Wait until the mailbox gets populated */ 5785427debSSumit Gargpoll_mailbox: 5885427debSSumit Garg cbz x0, 1f 5985427debSSumit Garg br x0 6085427debSSumit Garg1: 6185427debSSumit Garg wfe 6285427debSSumit Garg b poll_mailbox 6385427debSSumit Gargendfunc plat_secondary_cold_boot_setup 6485427debSSumit Garg 6585427debSSumit Garg/* 6685427debSSumit Garg * Find out whether the current cpu is the primary 6785427debSSumit Garg * cpu (applicable only after a cold boot) 6885427debSSumit Garg */ 6985427debSSumit Gargfunc plat_is_my_cpu_primary 7085427debSSumit Garg mov x9, x30 7185427debSSumit Garg bl plat_my_core_pos 7285427debSSumit Garg ldr x1, =SQ_BOOT_CFG_ADDR 7385427debSSumit Garg ldr x1, [x1] 7485427debSSumit Garg ubfx x1, x1, #PLAT_SQ_PRIMARY_CPU_SHIFT, \ 7585427debSSumit Garg #PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 7685427debSSumit Garg cmp x0, x1 7785427debSSumit Garg cset w0, eq 7885427debSSumit Garg ret x9 7985427debSSumit Gargendfunc plat_is_my_cpu_primary 8067b40070SSumit Garg 8167b40070SSumit Garg/* 8267b40070SSumit Garg * int plat_crash_console_init(void) 8367b40070SSumit Garg * Function to initialize the crash console 8467b40070SSumit Garg * without a C Runtime to print crash report. 8567b40070SSumit Garg * Clobber list : x0, x1, x2 8667b40070SSumit Garg */ 8767b40070SSumit Gargfunc plat_crash_console_init 8867b40070SSumit Garg mov_imm x0, PLAT_SQ_BOOT_UART_BASE 8967b40070SSumit Garg mov_imm x1, PLAT_SQ_BOOT_UART_CLK_IN_HZ 9067b40070SSumit Garg mov_imm x2, SQ_CONSOLE_BAUDRATE 9167b40070SSumit Garg b console_pl011_core_init 9267b40070SSumit Gargendfunc plat_crash_console_init 9367b40070SSumit Garg 9467b40070SSumit Garg/* 9567b40070SSumit Garg * int plat_crash_console_putc(int c) 9667b40070SSumit Garg * Function to print a character on the crash 9767b40070SSumit Garg * console without a C Runtime. 9867b40070SSumit Garg * Clobber list : x1, x2 9967b40070SSumit Garg */ 10067b40070SSumit Gargfunc plat_crash_console_putc 10167b40070SSumit Garg mov_imm x1, PLAT_SQ_BOOT_UART_BASE 10267b40070SSumit Garg b console_pl011_core_putc 10367b40070SSumit Gargendfunc plat_crash_console_putc 10467b40070SSumit Garg 10567b40070SSumit Garg/* 106831b0e98SJimmy Brisson * void plat_crash_console_flush(int c) 10767b40070SSumit Garg * Function to force a write of all buffered 10867b40070SSumit Garg * data that hasn't been output. 109831b0e98SJimmy Brisson * Out : void. 11067b40070SSumit Garg * Clobber list : x0, x1 11167b40070SSumit Garg */ 11267b40070SSumit Gargfunc plat_crash_console_flush 11367b40070SSumit Garg mov_imm x0, PLAT_SQ_BOOT_UART_BASE 11467b40070SSumit Garg b console_pl011_core_flush 11567b40070SSumit Gargendfunc plat_crash_console_flush 116