1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <gicv3.h> 9 #include <interrupt_props.h> 10 #include <platform.h> 11 #include <platform_def.h> 12 13 #include "sq_common.h" 14 15 static uintptr_t sq_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 16 17 static const interrupt_prop_t sq_interrupt_props[] = { 18 /* G0 interrupts */ 19 20 /* SGI0 */ 21 INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 22 GIC_INTR_CFG_EDGE), 23 /* SGI6 */ 24 INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 25 GIC_INTR_CFG_EDGE), 26 27 /* G1S interrupts */ 28 29 /* Timer */ 30 INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 31 GIC_INTR_CFG_LEVEL), 32 /* SGI1 */ 33 INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 34 GIC_INTR_CFG_EDGE), 35 /* SGI2 */ 36 INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 37 GIC_INTR_CFG_EDGE), 38 /* SGI3 */ 39 INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 40 GIC_INTR_CFG_EDGE), 41 /* SGI4 */ 42 INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 43 GIC_INTR_CFG_EDGE), 44 /* SGI5 */ 45 INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 46 GIC_INTR_CFG_EDGE), 47 /* SGI7 */ 48 INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 49 GIC_INTR_CFG_EDGE) 50 }; 51 52 static unsigned int sq_mpidr_to_core_pos(u_register_t mpidr) 53 { 54 return plat_core_pos_by_mpidr(mpidr); 55 } 56 57 static const struct gicv3_driver_data sq_gic_driver_data = { 58 .gicd_base = PLAT_SQ_GICD_BASE, 59 .gicr_base = PLAT_SQ_GICR_BASE, 60 .interrupt_props = sq_interrupt_props, 61 .interrupt_props_num = ARRAY_SIZE(sq_interrupt_props), 62 .rdistif_num = PLATFORM_CORE_COUNT, 63 .rdistif_base_addrs = sq_rdistif_base_addrs, 64 .mpidr_to_core_pos = sq_mpidr_to_core_pos, 65 }; 66 67 void sq_gic_driver_init(void) 68 { 69 gicv3_driver_init(&sq_gic_driver_data); 70 } 71 72 void sq_gic_init(void) 73 { 74 gicv3_distif_init(); 75 gicv3_rdistif_init(plat_my_core_pos()); 76 gicv3_cpuif_enable(plat_my_core_pos()); 77 } 78 79 void sq_gic_cpuif_enable(void) 80 { 81 gicv3_cpuif_enable(plat_my_core_pos()); 82 } 83 84 void sq_gic_cpuif_disable(void) 85 { 86 gicv3_cpuif_disable(plat_my_core_pos()); 87 } 88 89 void sq_gic_pcpu_init(void) 90 { 91 gicv3_rdistif_init(plat_my_core_pos()); 92 } 93