1*b529799fSSumit Garg /* 2*b529799fSSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*b529799fSSumit Garg * 4*b529799fSSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5*b529799fSSumit Garg */ 6*b529799fSSumit Garg 7*b529799fSSumit Garg #include <assert.h> 8*b529799fSSumit Garg #include <gicv3.h> 9*b529799fSSumit Garg #include <interrupt_props.h> 10*b529799fSSumit Garg #include <platform.h> 11*b529799fSSumit Garg #include <platform_def.h> 12*b529799fSSumit Garg 13*b529799fSSumit Garg #include "sq_common.h" 14*b529799fSSumit Garg 15*b529799fSSumit Garg static uintptr_t sq_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 16*b529799fSSumit Garg 17*b529799fSSumit Garg static const interrupt_prop_t sq_interrupt_props[] = { 18*b529799fSSumit Garg /* G0 interrupts */ 19*b529799fSSumit Garg 20*b529799fSSumit Garg /* SGI0 */ 21*b529799fSSumit Garg INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 22*b529799fSSumit Garg GIC_INTR_CFG_EDGE), 23*b529799fSSumit Garg /* SGI6 */ 24*b529799fSSumit Garg INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 25*b529799fSSumit Garg GIC_INTR_CFG_EDGE), 26*b529799fSSumit Garg 27*b529799fSSumit Garg /* G1S interrupts */ 28*b529799fSSumit Garg 29*b529799fSSumit Garg /* Timer */ 30*b529799fSSumit Garg INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 31*b529799fSSumit Garg GIC_INTR_CFG_LEVEL), 32*b529799fSSumit Garg /* SGI1 */ 33*b529799fSSumit Garg INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 34*b529799fSSumit Garg GIC_INTR_CFG_EDGE), 35*b529799fSSumit Garg /* SGI2 */ 36*b529799fSSumit Garg INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 37*b529799fSSumit Garg GIC_INTR_CFG_EDGE), 38*b529799fSSumit Garg /* SGI3 */ 39*b529799fSSumit Garg INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 40*b529799fSSumit Garg GIC_INTR_CFG_EDGE), 41*b529799fSSumit Garg /* SGI4 */ 42*b529799fSSumit Garg INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 43*b529799fSSumit Garg GIC_INTR_CFG_EDGE), 44*b529799fSSumit Garg /* SGI5 */ 45*b529799fSSumit Garg INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 46*b529799fSSumit Garg GIC_INTR_CFG_EDGE), 47*b529799fSSumit Garg /* SGI7 */ 48*b529799fSSumit Garg INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 49*b529799fSSumit Garg GIC_INTR_CFG_EDGE) 50*b529799fSSumit Garg }; 51*b529799fSSumit Garg 52*b529799fSSumit Garg static unsigned int sq_mpidr_to_core_pos(u_register_t mpidr) 53*b529799fSSumit Garg { 54*b529799fSSumit Garg return plat_core_pos_by_mpidr(mpidr); 55*b529799fSSumit Garg } 56*b529799fSSumit Garg 57*b529799fSSumit Garg static const struct gicv3_driver_data sq_gic_driver_data = { 58*b529799fSSumit Garg .gicd_base = PLAT_SQ_GICD_BASE, 59*b529799fSSumit Garg .gicr_base = PLAT_SQ_GICR_BASE, 60*b529799fSSumit Garg .interrupt_props = sq_interrupt_props, 61*b529799fSSumit Garg .interrupt_props_num = ARRAY_SIZE(sq_interrupt_props), 62*b529799fSSumit Garg .rdistif_num = PLATFORM_CORE_COUNT, 63*b529799fSSumit Garg .rdistif_base_addrs = sq_rdistif_base_addrs, 64*b529799fSSumit Garg .mpidr_to_core_pos = sq_mpidr_to_core_pos, 65*b529799fSSumit Garg }; 66*b529799fSSumit Garg 67*b529799fSSumit Garg void sq_gic_driver_init(void) 68*b529799fSSumit Garg { 69*b529799fSSumit Garg gicv3_driver_init(&sq_gic_driver_data); 70*b529799fSSumit Garg } 71*b529799fSSumit Garg 72*b529799fSSumit Garg void sq_gic_init(void) 73*b529799fSSumit Garg { 74*b529799fSSumit Garg gicv3_distif_init(); 75*b529799fSSumit Garg gicv3_rdistif_init(plat_my_core_pos()); 76*b529799fSSumit Garg gicv3_cpuif_enable(plat_my_core_pos()); 77*b529799fSSumit Garg } 78*b529799fSSumit Garg 79*b529799fSSumit Garg void sq_gic_cpuif_enable(void) 80*b529799fSSumit Garg { 81*b529799fSSumit Garg gicv3_cpuif_enable(plat_my_core_pos()); 82*b529799fSSumit Garg } 83*b529799fSSumit Garg 84*b529799fSSumit Garg void sq_gic_cpuif_disable(void) 85*b529799fSSumit Garg { 86*b529799fSSumit Garg gicv3_cpuif_disable(plat_my_core_pos()); 87*b529799fSSumit Garg } 88*b529799fSSumit Garg 89*b529799fSSumit Garg void sq_gic_pcpu_init(void) 90*b529799fSSumit Garg { 91*b529799fSSumit Garg gicv3_rdistif_init(plat_my_core_pos()); 92*b529799fSSumit Garg } 93