1b529799fSSumit Garg /* 2b529799fSSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3b529799fSSumit Garg * 4b529799fSSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5b529799fSSumit Garg */ 6b529799fSSumit Garg 7b529799fSSumit Garg #include <assert.h> 8*09d40e0eSAntonio Nino Diaz 9b529799fSSumit Garg #include <platform_def.h> 10b529799fSSumit Garg 11*09d40e0eSAntonio Nino Diaz #include <common/interrupt_props.h> 12*09d40e0eSAntonio Nino Diaz #include <drivers/arm/gicv3.h> 13*09d40e0eSAntonio Nino Diaz #include <plat/common/platform.h> 14*09d40e0eSAntonio Nino Diaz 15b529799fSSumit Garg #include "sq_common.h" 16b529799fSSumit Garg 17b529799fSSumit Garg static uintptr_t sq_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 18b529799fSSumit Garg 19b529799fSSumit Garg static const interrupt_prop_t sq_interrupt_props[] = { 20b529799fSSumit Garg /* G0 interrupts */ 21b529799fSSumit Garg 22b529799fSSumit Garg /* SGI0 */ 23b529799fSSumit Garg INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 24b529799fSSumit Garg GIC_INTR_CFG_EDGE), 25b529799fSSumit Garg /* SGI6 */ 26b529799fSSumit Garg INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 27b529799fSSumit Garg GIC_INTR_CFG_EDGE), 28b529799fSSumit Garg 29b529799fSSumit Garg /* G1S interrupts */ 30b529799fSSumit Garg 31b529799fSSumit Garg /* Timer */ 32b529799fSSumit Garg INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 33b529799fSSumit Garg GIC_INTR_CFG_LEVEL), 34b529799fSSumit Garg /* SGI1 */ 35b529799fSSumit Garg INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 36b529799fSSumit Garg GIC_INTR_CFG_EDGE), 37b529799fSSumit Garg /* SGI2 */ 38b529799fSSumit Garg INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 39b529799fSSumit Garg GIC_INTR_CFG_EDGE), 40b529799fSSumit Garg /* SGI3 */ 41b529799fSSumit Garg INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 42b529799fSSumit Garg GIC_INTR_CFG_EDGE), 43b529799fSSumit Garg /* SGI4 */ 44b529799fSSumit Garg INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 45b529799fSSumit Garg GIC_INTR_CFG_EDGE), 46b529799fSSumit Garg /* SGI5 */ 47b529799fSSumit Garg INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 48b529799fSSumit Garg GIC_INTR_CFG_EDGE), 49b529799fSSumit Garg /* SGI7 */ 50b529799fSSumit Garg INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, 51b529799fSSumit Garg GIC_INTR_CFG_EDGE) 52b529799fSSumit Garg }; 53b529799fSSumit Garg 54b529799fSSumit Garg static unsigned int sq_mpidr_to_core_pos(u_register_t mpidr) 55b529799fSSumit Garg { 56b529799fSSumit Garg return plat_core_pos_by_mpidr(mpidr); 57b529799fSSumit Garg } 58b529799fSSumit Garg 59b529799fSSumit Garg static const struct gicv3_driver_data sq_gic_driver_data = { 60b529799fSSumit Garg .gicd_base = PLAT_SQ_GICD_BASE, 61b529799fSSumit Garg .gicr_base = PLAT_SQ_GICR_BASE, 62b529799fSSumit Garg .interrupt_props = sq_interrupt_props, 63b529799fSSumit Garg .interrupt_props_num = ARRAY_SIZE(sq_interrupt_props), 64b529799fSSumit Garg .rdistif_num = PLATFORM_CORE_COUNT, 65b529799fSSumit Garg .rdistif_base_addrs = sq_rdistif_base_addrs, 66b529799fSSumit Garg .mpidr_to_core_pos = sq_mpidr_to_core_pos, 67b529799fSSumit Garg }; 68b529799fSSumit Garg 69b529799fSSumit Garg void sq_gic_driver_init(void) 70b529799fSSumit Garg { 71b529799fSSumit Garg gicv3_driver_init(&sq_gic_driver_data); 72b529799fSSumit Garg } 73b529799fSSumit Garg 74b529799fSSumit Garg void sq_gic_init(void) 75b529799fSSumit Garg { 76b529799fSSumit Garg gicv3_distif_init(); 77b529799fSSumit Garg gicv3_rdistif_init(plat_my_core_pos()); 78b529799fSSumit Garg gicv3_cpuif_enable(plat_my_core_pos()); 79b529799fSSumit Garg } 80b529799fSSumit Garg 81b529799fSSumit Garg void sq_gic_cpuif_enable(void) 82b529799fSSumit Garg { 83b529799fSSumit Garg gicv3_cpuif_enable(plat_my_core_pos()); 84b529799fSSumit Garg } 85b529799fSSumit Garg 86b529799fSSumit Garg void sq_gic_cpuif_disable(void) 87b529799fSSumit Garg { 88b529799fSSumit Garg gicv3_cpuif_disable(plat_my_core_pos()); 89b529799fSSumit Garg } 90b529799fSSumit Garg 91b529799fSSumit Garg void sq_gic_pcpu_init(void) 92b529799fSSumit Garg { 93b529799fSSumit Garg gicv3_rdistif_init(plat_my_core_pos()); 94b529799fSSumit Garg } 95