1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/pl011.h> 16 #include <lib/mmio.h> 17 18 #include <sq_common.h> 19 20 static console_pl011_t console; 21 static entry_point_info_t bl32_image_ep_info; 22 static entry_point_info_t bl33_image_ep_info; 23 24 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START); 25 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END); 26 IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_LMA__, SPM_SHIM_EXCEPTIONS_LMA); 27 28 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 29 { 30 assert(sec_state_is_valid(type)); 31 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; 32 } 33 34 /******************************************************************************* 35 * Gets SPSR for BL32 entry 36 ******************************************************************************/ 37 uint32_t sq_get_spsr_for_bl32_entry(void) 38 { 39 /* 40 * The Secure Payload Dispatcher service is responsible for 41 * setting the SPSR prior to entry into the BL32 image. 42 */ 43 return 0; 44 } 45 46 /******************************************************************************* 47 * Gets SPSR for BL33 entry 48 ******************************************************************************/ 49 uint32_t sq_get_spsr_for_bl33_entry(void) 50 { 51 unsigned long el_status; 52 unsigned int mode; 53 uint32_t spsr; 54 55 /* Figure out what mode we enter the non-secure world in */ 56 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 57 el_status &= ID_AA64PFR0_ELX_MASK; 58 59 mode = (el_status) ? MODE_EL2 : MODE_EL1; 60 61 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 62 return spsr; 63 } 64 65 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 66 u_register_t arg2, u_register_t arg3) 67 { 68 /* Initialize the console to provide early debug support */ 69 (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, 70 PLAT_SQ_BOOT_UART_CLK_IN_HZ, 71 SQ_CONSOLE_BAUDRATE, &console); 72 73 console_set_scope(&console.console, CONSOLE_FLAG_BOOT | 74 CONSOLE_FLAG_RUNTIME); 75 76 /* There are no parameters from BL2 if BL31 is a reset vector */ 77 assert(arg0 == 0U); 78 assert(arg1 == 0U); 79 80 /* Initialize power controller before setting up topology */ 81 plat_sq_pwrc_setup(); 82 83 #ifdef SPD_opteed 84 struct draminfo di = {0}; 85 86 scpi_get_draminfo(&di); 87 88 /* 89 * Check if OP-TEE has been loaded in Secure RAM allocated 90 * from DRAM1 region 91 */ 92 if ((di.base1 + di.size1) <= BL32_BASE) { 93 NOTICE("OP-TEE has been loaded by SCP firmware\n"); 94 /* Populate entry point information for BL32 */ 95 SET_PARAM_HEAD(&bl32_image_ep_info, 96 PARAM_EP, 97 VERSION_1, 98 0); 99 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 100 bl32_image_ep_info.pc = BL32_BASE; 101 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); 102 } else { 103 NOTICE("OP-TEE has not been loaded by SCP firmware\n"); 104 } 105 #endif /* SPD_opteed */ 106 107 /* Populate entry point information for BL33 */ 108 SET_PARAM_HEAD(&bl33_image_ep_info, 109 PARAM_EP, 110 VERSION_1, 111 0); 112 /* 113 * Tell BL31 where the non-trusted software image 114 * is located and the entry state information 115 */ 116 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 117 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); 118 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 119 } 120 121 static void sq_configure_sys_timer(void) 122 { 123 unsigned int reg_val; 124 125 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 126 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 127 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 128 mmio_write_32(SQ_SYS_TIMCTL_BASE + 129 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); 130 131 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); 132 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 133 } 134 135 void bl31_platform_setup(void) 136 { 137 /* Initialize the CCN interconnect */ 138 plat_sq_interconnect_init(); 139 plat_sq_interconnect_enter_coherency(); 140 141 /* Initialize the GIC driver, cpu and distributor interfaces */ 142 sq_gic_driver_init(); 143 sq_gic_init(); 144 145 /* Enable and initialize the System level generic timer */ 146 mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF, 147 CNTCR_FCREQ(0U) | CNTCR_EN); 148 149 /* Allow access to the System counter timer module */ 150 sq_configure_sys_timer(); 151 } 152 153 void bl31_plat_runtime_setup(void) 154 { 155 struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE; 156 157 scpi_get_draminfo(di); 158 } 159 160 void bl31_plat_arch_setup(void) 161 { 162 static const mmap_region_t secure_partition_mmap[] = { 163 #if ENABLE_SPM && SPM_DEPRECATED 164 MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, 165 PLAT_SPM_BUF_SIZE, 166 MT_RW_DATA | MT_SECURE), 167 MAP_REGION_FLAT(PLAT_SQ_SP_PRIV_BASE, 168 PLAT_SQ_SP_PRIV_SIZE, 169 MT_RW_DATA | MT_SECURE), 170 #endif 171 {0}, 172 }; 173 174 sq_mmap_setup(BL31_BASE, BL31_SIZE, secure_partition_mmap); 175 enable_mmu_el3(XLAT_TABLE_NC); 176 177 #if ENABLE_SPM && SPM_DEPRECATED 178 memcpy((void *)SPM_SHIM_EXCEPTIONS_START, 179 (void *)SPM_SHIM_EXCEPTIONS_LMA, 180 (uintptr_t)SPM_SHIM_EXCEPTIONS_END - 181 (uintptr_t)SPM_SHIM_EXCEPTIONS_START); 182 #endif 183 } 184 185 void bl31_plat_enable_mmu(uint32_t flags) 186 { 187 enable_mmu_el3(flags | XLAT_TABLE_NC); 188 } 189 190 unsigned int plat_get_syscnt_freq2(void) 191 { 192 unsigned int counter_base_frequency; 193 194 /* Read the frequency from Frequency modes table */ 195 counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF); 196 197 /* The first entry of the frequency modes table must not be 0 */ 198 if (counter_base_frequency == 0) 199 panic(); 200 201 return counter_base_frequency; 202 } 203