1*48ab3904SJassi Brar /*
2*48ab3904SJassi Brar * Copyright (c) 2022, Socionext Inc. All rights reserved.
3*48ab3904SJassi Brar *
4*48ab3904SJassi Brar * SPDX-License-Identifier: BSD-3-Clause
5*48ab3904SJassi Brar */
6*48ab3904SJassi Brar
7*48ab3904SJassi Brar #include <errno.h>
8*48ab3904SJassi Brar
9*48ab3904SJassi Brar #include <common/bl_common.h>
10*48ab3904SJassi Brar #include <common/debug.h>
11*48ab3904SJassi Brar #include <common/desc_image_load.h>
12*48ab3904SJassi Brar #include <common/image_decompress.h>
13*48ab3904SJassi Brar #include <drivers/arm/pl011.h>
14*48ab3904SJassi Brar #include <drivers/io/io_storage.h>
15*48ab3904SJassi Brar #include <lib/xlat_tables/xlat_tables_v2.h>
16*48ab3904SJassi Brar #include <plat/common/platform.h>
17*48ab3904SJassi Brar
18*48ab3904SJassi Brar #include <platform_def.h>
19*48ab3904SJassi Brar #include <sq_common.h>
20*48ab3904SJassi Brar
21*48ab3904SJassi Brar static console_t console;
22*48ab3904SJassi Brar
bl2_el3_early_platform_setup(u_register_t x0,u_register_t x1,u_register_t x2,u_register_t x3)23*48ab3904SJassi Brar void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
24*48ab3904SJassi Brar u_register_t x2, u_register_t x3)
25*48ab3904SJassi Brar {
26*48ab3904SJassi Brar /* Initialize the console to provide early debug support */
27*48ab3904SJassi Brar (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
28*48ab3904SJassi Brar PLAT_SQ_BOOT_UART_CLK_IN_HZ,
29*48ab3904SJassi Brar SQ_CONSOLE_BAUDRATE, &console);
30*48ab3904SJassi Brar console_set_scope(&console, CONSOLE_FLAG_BOOT);
31*48ab3904SJassi Brar }
32*48ab3904SJassi Brar
bl2_el3_plat_arch_setup(void)33*48ab3904SJassi Brar void bl2_el3_plat_arch_setup(void)
34*48ab3904SJassi Brar {
35*48ab3904SJassi Brar int ret;
36*48ab3904SJassi Brar
37*48ab3904SJassi Brar sq_mmap_setup(BL2_BASE, BL2_SIZE, NULL);
38*48ab3904SJassi Brar
39*48ab3904SJassi Brar ret = sq_io_setup();
40*48ab3904SJassi Brar if (ret) {
41*48ab3904SJassi Brar ERROR("failed to setup io devices\n");
42*48ab3904SJassi Brar plat_error_handler(ret);
43*48ab3904SJassi Brar }
44*48ab3904SJassi Brar }
45*48ab3904SJassi Brar
bl2_platform_setup(void)46*48ab3904SJassi Brar void bl2_platform_setup(void)
47*48ab3904SJassi Brar {
48*48ab3904SJassi Brar }
49*48ab3904SJassi Brar
plat_flush_next_bl_params(void)50*48ab3904SJassi Brar void plat_flush_next_bl_params(void)
51*48ab3904SJassi Brar {
52*48ab3904SJassi Brar flush_bl_params_desc();
53*48ab3904SJassi Brar }
54*48ab3904SJassi Brar
plat_get_bl_image_load_info(void)55*48ab3904SJassi Brar bl_load_info_t *plat_get_bl_image_load_info(void)
56*48ab3904SJassi Brar {
57*48ab3904SJassi Brar return get_bl_load_info_from_mem_params_desc();
58*48ab3904SJassi Brar }
59*48ab3904SJassi Brar
plat_get_next_bl_params(void)60*48ab3904SJassi Brar bl_params_t *plat_get_next_bl_params(void)
61*48ab3904SJassi Brar {
62*48ab3904SJassi Brar return get_next_bl_params_from_mem_params_desc();
63*48ab3904SJassi Brar }
64*48ab3904SJassi Brar
bl2_plat_preload_setup(void)65*48ab3904SJassi Brar void bl2_plat_preload_setup(void)
66*48ab3904SJassi Brar {
67*48ab3904SJassi Brar }
68*48ab3904SJassi Brar
bl2_plat_handle_pre_image_load(unsigned int image_id)69*48ab3904SJassi Brar int bl2_plat_handle_pre_image_load(unsigned int image_id)
70*48ab3904SJassi Brar {
71*48ab3904SJassi Brar struct image_info *image_info;
72*48ab3904SJassi Brar
73*48ab3904SJassi Brar image_info = sq_get_image_info(image_id);
74*48ab3904SJassi Brar
75*48ab3904SJassi Brar return mmap_add_dynamic_region(image_info->image_base,
76*48ab3904SJassi Brar image_info->image_base,
77*48ab3904SJassi Brar image_info->image_max_size,
78*48ab3904SJassi Brar MT_MEMORY | MT_RW | MT_NS);
79*48ab3904SJassi Brar }
80*48ab3904SJassi Brar
bl2_plat_handle_post_image_load(unsigned int image_id)81*48ab3904SJassi Brar int bl2_plat_handle_post_image_load(unsigned int image_id)
82*48ab3904SJassi Brar {
83*48ab3904SJassi Brar return 0;
84*48ab3904SJassi Brar }
85