1# 2# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7override PROGRAMMABLE_RESET_ADDRESS := 1 8override USE_COHERENT_MEM := 1 9override SEPARATE_CODE_AND_RODATA := 1 10override ENABLE_SVE_FOR_NS := 0 11# Enable workarounds for selected Cortex-A53 erratas. 12ERRATA_A53_855873 := 1 13 14ifeq (${RESET_TO_BL31}, 1) 15override RESET_TO_BL31 := 1 16override TRUSTED_BOARD_BOOT := 0 17SQ_USE_SCMI_DRIVER ?= 0 18else 19override RESET_TO_BL31 := 0 20override RESET_TO_BL2 := 1 21SQ_USE_SCMI_DRIVER := 1 22BL2_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 23endif 24 25# Libraries 26include lib/xlat_tables_v2/xlat_tables.mk 27 28ifeq (${TRANSFER_LIST}, 1) 29include lib/transfer_list/transfer_list.mk 30endif 31 32ifeq (${HOB_LIST}, 1) 33include lib/hob/hob.mk 34endif 35 36PLAT_PATH := plat/socionext/synquacer 37PLAT_INCLUDES := -I$(PLAT_PATH)/include \ 38 -I$(PLAT_PATH)/drivers/scpi \ 39 -I$(PLAT_PATH)/drivers/mhu \ 40 -Idrivers/arm/css/scmi \ 41 -Idrivers/arm/css/scmi/vendor 42 43PLAT_BL_COMMON_SOURCES += $(PLAT_PATH)/sq_helpers.S \ 44 drivers/arm/pl011/aarch64/pl011_console.S \ 45 drivers/delay_timer/delay_timer.c \ 46 drivers/delay_timer/generic_delay_timer.c \ 47 lib/cpus/aarch64/cortex_a53.S \ 48 $(PLAT_PATH)/sq_xlat_setup.c \ 49 ${XLAT_TABLES_LIB_SRCS} 50 51# Include GICv3 driver files 52include drivers/arm/gic/v3/gicv3.mk 53 54ifneq (${RESET_TO_BL31}, 1) 55BL2_SOURCES += common/desc_image_load.c \ 56 drivers/io/io_fip.c \ 57 drivers/io/io_memmap.c \ 58 drivers/io/io_storage.c \ 59 $(PLAT_PATH)/sq_bl2_setup.c \ 60 $(PLAT_PATH)/sq_image_desc.c \ 61 $(PLAT_PATH)/sq_io_storage.c 62 63ifeq (${TRUSTED_BOARD_BOOT},1) 64include drivers/auth/mbedtls/mbedtls_crypto.mk 65include drivers/auth/mbedtls/mbedtls_x509.mk 66BL2_SOURCES += drivers/auth/auth_mod.c \ 67 drivers/auth/crypto_mod.c \ 68 drivers/auth/img_parser_mod.c \ 69 drivers/auth/tbbr/tbbr_cot_common.c \ 70 drivers/auth/tbbr/tbbr_cot_bl2.c \ 71 plat/common/tbbr/plat_tbbr.c \ 72 $(PLAT_PATH)/sq_rotpk.S \ 73 $(PLAT_PATH)/sq_tbbr.c 74 75ROT_KEY = $(BUILD_PLAT)/rot_key.pem 76ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin 77 78$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"')) 79$(BUILD_PLAT)/bl2/sq_rotpk.o: $(ROTPK_HASH) 80 81certificates: $(ROT_KEY) 82$(ROT_KEY): | $$(@D)/ 83 $(s)echo " OPENSSL $@" 84 $(q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null 85 86$(ROTPK_HASH): $(ROT_KEY) | $$(@D)/ 87 $(s)echo " OPENSSL $@" 88 $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\ 89 ${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null 90 91endif # TRUSTED_BOARD_BOOT 92endif 93 94BL31_SOURCES += drivers/arm/ccn/ccn.c \ 95 ${GICV3_SOURCES} \ 96 plat/common/plat_gicv3.c \ 97 plat/common/plat_psci_common.c \ 98 $(PLAT_PATH)/sq_bl31_setup.c \ 99 $(PLAT_PATH)/sq_ccn.c \ 100 $(PLAT_PATH)/sq_topology.c \ 101 $(PLAT_PATH)/sq_psci.c \ 102 $(PLAT_PATH)/sq_gicv3.c \ 103 $(PLAT_PATH)/drivers/scp/sq_scp.c 104 105ifeq (${SQ_USE_SCMI_DRIVER},0) 106BL31_SOURCES += $(PLAT_PATH)/drivers/scpi/sq_scpi.c \ 107 $(PLAT_PATH)/drivers/mhu/sq_mhu.c 108else 109BL31_SOURCES += $(PLAT_PATH)/drivers/scp/sq_scmi.c \ 110 drivers/arm/css/scmi/scmi_common.c \ 111 drivers/arm/css/scmi/scmi_pwr_dmn_proto.c \ 112 drivers/arm/css/scmi/scmi_sys_pwr_proto.c \ 113 drivers/arm/css/scmi/vendor/scmi_sq.c \ 114 drivers/arm/css/mhu/css_mhu_doorbell.c 115endif 116 117ifeq (${SPM_MM},1) 118$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 119 120BL31_SOURCES += $(PLAT_PATH)/sq_spm.c 121endif 122 123ifeq (${SQ_USE_SCMI_DRIVER},1) 124$(eval $(call add_define,SQ_USE_SCMI_DRIVER)) 125endif 126