1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* CPU topology */ 14 #define PLAT_MAX_CORES_PER_CLUSTER 2 15 #define PLAT_CLUSTER_COUNT 12 16 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 17 PLAT_MAX_CORES_PER_CLUSTER) 18 19 #define PLAT_MAX_PWR_LVL U(1) 20 #define PLAT_MAX_RET_STATE U(1) 21 #define PLAT_MAX_OFF_STATE U(2) 22 23 #define SQ_LOCAL_STATE_RUN 0 24 #define SQ_LOCAL_STATE_RET 1 25 #define SQ_LOCAL_STATE_OFF 2 26 27 #define CACHE_WRITEBACK_SHIFT 6 28 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 29 30 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 31 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 32 #define MAX_XLAT_TABLES 8 33 #define MAX_MMAP_REGIONS 8 34 35 #define PLATFORM_STACK_SIZE 0x400 36 37 #define BL31_BASE 0x04000000 38 #define BL31_SIZE 0x00080000 39 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 40 41 #define BL32_BASE 0xfc000000 42 #define BL32_SIZE 0x03c00000 43 #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 44 45 #define PLAT_SQ_CCN_BASE 0x32000000 46 #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 47 0, /* Cluster 0 */ \ 48 18, /* Cluster 1 */ \ 49 11, /* Cluster 2 */ \ 50 29, /* Cluster 3 */ \ 51 35, /* Cluster 4 */ \ 52 17, /* Cluster 5 */ \ 53 12, /* Cluster 6 */ \ 54 30, /* Cluster 7 */ \ 55 14, /* Cluster 8 */ \ 56 32, /* Cluster 9 */ \ 57 15, /* Cluster 10 */ \ 58 33 /* Cluster 11 */ 59 60 /* UART related constants */ 61 #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 62 #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 63 #define SQ_CONSOLE_BAUDRATE 115200 64 65 #define SQ_SYS_CNTCTL_BASE 0x2a430000 66 67 #define SQ_SYS_TIMCTL_BASE 0x2a810000 68 #define PLAT_SQ_NSTIMER_FRAME_ID 0 69 70 #define DRAMINFO_BASE 0x2E00FFC0 71 72 #define PLAT_SQ_MHU_BASE 0x45000000 73 74 #define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000 75 #define SCPI_CMD_GET_DRAMINFO 0x1 76 77 #define SQ_BOOT_CFG_ADDR 0x45410000 78 #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 79 #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 80 81 #define PLAT_SQ_GICD_BASE 0x30000000 82 #define PLAT_SQ_GICR_BASE 0x30400000 83 84 #define PLAT_SQ_GPIO_BASE 0x51000000 85 86 #define PLAT_SPM_BUF_BASE (BL32_LIMIT - 32 * PLAT_SPM_BUF_SIZE) 87 #define PLAT_SPM_BUF_SIZE ULL(0x10000) 88 #define PLAT_SPM_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \ 89 PLAT_SPM_BUF_BASE, \ 90 PLAT_SPM_BUF_SIZE, \ 91 MT_RO_DATA | MT_SECURE | \ 92 MT_USER, PAGE_SIZE) 93 94 #define PLAT_SP_IMAGE_NS_BUF_BASE BL32_LIMIT 95 #define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x200000) 96 #define PLAT_SP_IMAGE_NS_BUF_MMAP MAP_REGION2(PLAT_SP_IMAGE_NS_BUF_BASE, \ 97 PLAT_SP_IMAGE_NS_BUF_BASE, \ 98 PLAT_SP_IMAGE_NS_BUF_SIZE, \ 99 MT_RW_DATA | MT_NS | \ 100 MT_USER, PAGE_SIZE) 101 102 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000) 103 #define PLAT_SP_IMAGE_STACK_SIZE (32 * PLAT_SP_IMAGE_STACK_PCPU_SIZE) 104 #define PLAT_SP_IMAGE_STACK_BASE (PLAT_SQ_SP_HEAP_BASE + PLAT_SQ_SP_HEAP_SIZE) 105 106 #define PLAT_SQ_SP_IMAGE_SIZE ULL(0x200000) 107 #define PLAT_SQ_SP_IMAGE_MMAP MAP_REGION2(BL32_BASE, BL32_BASE, \ 108 PLAT_SQ_SP_IMAGE_SIZE, \ 109 MT_CODE | MT_SECURE | \ 110 MT_USER, PAGE_SIZE) 111 112 #define PLAT_SQ_SP_HEAP_BASE (BL32_BASE + PLAT_SQ_SP_IMAGE_SIZE) 113 #define PLAT_SQ_SP_HEAP_SIZE ULL(0x800000) 114 115 #define PLAT_SQ_SP_IMAGE_RW_MMAP MAP_REGION2(PLAT_SQ_SP_HEAP_BASE, \ 116 PLAT_SQ_SP_HEAP_BASE, \ 117 (PLAT_SQ_SP_HEAP_SIZE + \ 118 PLAT_SP_IMAGE_STACK_SIZE), \ 119 MT_RW_DATA | MT_SECURE | \ 120 MT_USER, PAGE_SIZE) 121 122 #define PLAT_SQ_SP_PRIV_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 123 PLAT_SP_IMAGE_STACK_SIZE) 124 #define PLAT_SQ_SP_PRIV_SIZE ULL(0x40000) 125 126 #define PLAT_SP_PRI 0x20 127 #define PLAT_PRI_BITS 2 128 #define PLAT_SPM_COOKIE_0 ULL(0) 129 #define PLAT_SPM_COOKIE_1 ULL(0) 130 131 /* Total number of memory regions with distinct properties */ 132 #define PLAT_SP_IMAGE_NUM_MEM_REGIONS 6 133 134 #define PLAT_SP_IMAGE_MMAP_REGIONS 30 135 #define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20 136 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME "sp_xlat_table" 137 138 #define PLAT_SQ_UART1_BASE PLAT_SQ_BOOT_UART_BASE 139 #define PLAT_SQ_UART1_SIZE ULL(0x1000) 140 #define PLAT_SQ_UART1_MMAP MAP_REGION_FLAT(PLAT_SQ_UART1_BASE, \ 141 PLAT_SQ_UART1_SIZE, \ 142 MT_DEVICE | MT_RW | \ 143 MT_NS | MT_PRIVILEGED) 144 145 #define PLAT_SQ_PERIPH_BASE 0x50000000 146 #define PLAT_SQ_PERIPH_SIZE ULL(0x8000000) 147 #define PLAT_SQ_PERIPH_MMAP MAP_REGION_FLAT(PLAT_SQ_PERIPH_BASE, \ 148 PLAT_SQ_PERIPH_SIZE, \ 149 MT_DEVICE | MT_RW | \ 150 MT_NS | MT_USER) 151 152 #define PLAT_SQ_FLASH_BASE 0x08000000 153 #define PLAT_SQ_FLASH_SIZE ULL(0x8000000) 154 #define PLAT_SQ_FLASH_MMAP MAP_REGION_FLAT(PLAT_SQ_FLASH_BASE, \ 155 PLAT_SQ_FLASH_SIZE, \ 156 MT_DEVICE | MT_RW | \ 157 MT_NS | MT_USER) 158 159 #endif /* PLATFORM_DEF_H */ 160