1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <common_def.h> 11 12 /* CPU topology */ 13 #define PLAT_MAX_CORES_PER_CLUSTER 2 14 #define PLAT_CLUSTER_COUNT 12 15 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 16 PLAT_MAX_CORES_PER_CLUSTER) 17 18 #define PLAT_MAX_PWR_LVL 1 19 #define PLAT_MAX_RET_STATE 1 20 #define PLAT_MAX_OFF_STATE 2 21 22 #define SQ_LOCAL_STATE_RUN 0 23 #define SQ_LOCAL_STATE_RET 1 24 #define SQ_LOCAL_STATE_OFF 2 25 26 #define CACHE_WRITEBACK_SHIFT 6 27 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 28 29 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 30 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 31 #define MAX_XLAT_TABLES 4 32 #define MAX_MMAP_REGIONS 6 33 34 #define PLATFORM_STACK_SIZE 0x400 35 36 #define BL31_BASE 0x04000000 37 #define BL31_SIZE 0x00080000 38 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 39 40 #define PLAT_SQ_CCN_BASE 0x32000000 41 #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 42 0, /* Cluster 0 */ \ 43 18, /* Cluster 1 */ \ 44 11, /* Cluster 2 */ \ 45 29, /* Cluster 3 */ \ 46 35, /* Cluster 4 */ \ 47 17, /* Cluster 5 */ \ 48 12, /* Cluster 6 */ \ 49 30, /* Cluster 7 */ \ 50 14, /* Cluster 8 */ \ 51 32, /* Cluster 9 */ \ 52 15, /* Cluster 10 */ \ 53 33 /* Cluster 11 */ 54 55 /* UART related constants */ 56 #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 57 #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 58 #define SQ_CONSOLE_BAUDRATE 115200 59 60 #define SQ_SYS_CNTCTL_BASE 0x2a430000 61 62 #define SQ_SYS_TIMCTL_BASE 0x2a810000 63 #define PLAT_SQ_NSTIMER_FRAME_ID 0 64 65 #define DRAMINFO_BASE 0x2E00FFC0 66 67 #define PLAT_SQ_MHU_BASE 0x45000000 68 69 #define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000 70 #define SCPI_CMD_GET_DRAMINFO 0x1 71 72 #define SQ_BOOT_CFG_ADDR 0x45410000 73 #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 74 #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 75 76 #define PLAT_SQ_GICD_BASE 0x30000000 77 #define PLAT_SQ_GICR_BASE 0x30400000 78 79 #define PLAT_SQ_GPIO_BASE 0x51000000 80 81 #endif /* __PLATFORM_DEF_H__ */ 82