1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <common_def.h> 11 12 /* CPU topology */ 13 #define PLAT_MAX_CORES_PER_CLUSTER 2 14 #define PLAT_CLUSTER_COUNT 12 15 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 16 PLAT_MAX_CORES_PER_CLUSTER) 17 18 #define CACHE_WRITEBACK_SHIFT 6 19 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 20 21 #define PLATFORM_STACK_SIZE 0x400 22 23 #define BL31_BASE 0x04000000 24 #define BL31_SIZE 0x00080000 25 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 26 27 #define PLAT_SQ_CCN_BASE 0x32000000 28 #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 29 0, /* Cluster 0 */ \ 30 18, /* Cluster 1 */ \ 31 11, /* Cluster 2 */ \ 32 29, /* Cluster 3 */ \ 33 35, /* Cluster 4 */ \ 34 17, /* Cluster 5 */ \ 35 12, /* Cluster 6 */ \ 36 30, /* Cluster 7 */ \ 37 14, /* Cluster 8 */ \ 38 32, /* Cluster 9 */ \ 39 15, /* Cluster 10 */ \ 40 33 /* Cluster 11 */ 41 42 /* UART related constants */ 43 #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 44 #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 45 #define SQ_CONSOLE_BAUDRATE 115200 46 47 #define SQ_BOOT_CFG_ADDR 0x45410000 48 #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 49 #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 50 51 #endif /* __PLATFORM_DEF_H__ */ 52