1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <common_def.h> 11 12 /* CPU topology */ 13 #define PLAT_MAX_CORES_PER_CLUSTER 2 14 #define PLAT_CLUSTER_COUNT 12 15 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 16 PLAT_MAX_CORES_PER_CLUSTER) 17 18 #define CACHE_WRITEBACK_SHIFT 6 19 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 20 21 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 22 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 23 #define MAX_XLAT_TABLES 4 24 #define MAX_MMAP_REGIONS 6 25 26 #define PLATFORM_STACK_SIZE 0x400 27 28 #define BL31_BASE 0x04000000 29 #define BL31_SIZE 0x00080000 30 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 31 32 #define PLAT_SQ_CCN_BASE 0x32000000 33 #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 34 0, /* Cluster 0 */ \ 35 18, /* Cluster 1 */ \ 36 11, /* Cluster 2 */ \ 37 29, /* Cluster 3 */ \ 38 35, /* Cluster 4 */ \ 39 17, /* Cluster 5 */ \ 40 12, /* Cluster 6 */ \ 41 30, /* Cluster 7 */ \ 42 14, /* Cluster 8 */ \ 43 32, /* Cluster 9 */ \ 44 15, /* Cluster 10 */ \ 45 33 /* Cluster 11 */ 46 47 /* UART related constants */ 48 #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 49 #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 50 #define SQ_CONSOLE_BAUDRATE 115200 51 52 #define SQ_SYS_CNTCTL_BASE 0x2a430000 53 54 #define SQ_SYS_TIMCTL_BASE 0x2a810000 55 #define PLAT_SQ_NSTIMER_FRAME_ID 0 56 57 #define PLAT_SQ_MHU_BASE 0x45000000 58 59 #define SQ_BOOT_CFG_ADDR 0x45410000 60 #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 61 #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 62 63 #define PLAT_SQ_GICD_BASE 0x30000000 64 #define PLAT_SQ_GICR_BASE 0x30400000 65 66 #endif /* __PLATFORM_DEF_H__ */ 67