1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <common_def.h> 11 12 /* CPU topology */ 13 #define PLAT_MAX_CORES_PER_CLUSTER 2 14 #define PLAT_CLUSTER_COUNT 12 15 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 16 PLAT_MAX_CORES_PER_CLUSTER) 17 18 #define CACHE_WRITEBACK_SHIFT 6 19 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 20 21 #define PLATFORM_STACK_SIZE 0x400 22 23 #define BL31_BASE 0x04000000 24 #define BL31_SIZE 0x00080000 25 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 26 27 /* UART related constants */ 28 #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 29 #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 30 #define SQ_CONSOLE_BAUDRATE 115200 31 32 #define SQ_BOOT_CFG_ADDR 0x45410000 33 #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 34 #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 35 36 #endif /* __PLATFORM_DEF_H__ */ 37