1c35d59a3SSumit Garg /* 2c35d59a3SSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3c35d59a3SSumit Garg * 4c35d59a3SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5c35d59a3SSumit Garg */ 6c35d59a3SSumit Garg 7c35d59a3SSumit Garg #ifndef __PLATFORM_DEF_H__ 8c35d59a3SSumit Garg #define __PLATFORM_DEF_H__ 9c35d59a3SSumit Garg 10c35d59a3SSumit Garg #include <common_def.h> 11c35d59a3SSumit Garg 12007a7a33SSumit Garg /* CPU topology */ 13007a7a33SSumit Garg #define PLAT_MAX_CORES_PER_CLUSTER 2 14007a7a33SSumit Garg #define PLAT_CLUSTER_COUNT 12 15007a7a33SSumit Garg #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 16007a7a33SSumit Garg PLAT_MAX_CORES_PER_CLUSTER) 17007a7a33SSumit Garg 18c35d59a3SSumit Garg #define CACHE_WRITEBACK_SHIFT 6 19c35d59a3SSumit Garg #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 20c35d59a3SSumit Garg 218cd37d7bSSumit Garg #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 228cd37d7bSSumit Garg #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 238cd37d7bSSumit Garg #define MAX_XLAT_TABLES 4 248cd37d7bSSumit Garg #define MAX_MMAP_REGIONS 6 258cd37d7bSSumit Garg 26c35d59a3SSumit Garg #define PLATFORM_STACK_SIZE 0x400 27c35d59a3SSumit Garg 28c35d59a3SSumit Garg #define BL31_BASE 0x04000000 29c35d59a3SSumit Garg #define BL31_SIZE 0x00080000 30c35d59a3SSumit Garg #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 31c35d59a3SSumit Garg 320eb275c9SSumit Garg #define PLAT_SQ_CCN_BASE 0x32000000 330eb275c9SSumit Garg #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 340eb275c9SSumit Garg 0, /* Cluster 0 */ \ 350eb275c9SSumit Garg 18, /* Cluster 1 */ \ 360eb275c9SSumit Garg 11, /* Cluster 2 */ \ 370eb275c9SSumit Garg 29, /* Cluster 3 */ \ 380eb275c9SSumit Garg 35, /* Cluster 4 */ \ 390eb275c9SSumit Garg 17, /* Cluster 5 */ \ 400eb275c9SSumit Garg 12, /* Cluster 6 */ \ 410eb275c9SSumit Garg 30, /* Cluster 7 */ \ 420eb275c9SSumit Garg 14, /* Cluster 8 */ \ 430eb275c9SSumit Garg 32, /* Cluster 9 */ \ 440eb275c9SSumit Garg 15, /* Cluster 10 */ \ 450eb275c9SSumit Garg 33 /* Cluster 11 */ 460eb275c9SSumit Garg 4767b40070SSumit Garg /* UART related constants */ 4867b40070SSumit Garg #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 4967b40070SSumit Garg #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 5067b40070SSumit Garg #define SQ_CONSOLE_BAUDRATE 115200 5167b40070SSumit Garg 525931fdacSSumit Garg #define SQ_SYS_CNTCTL_BASE 0x2a430000 535931fdacSSumit Garg 545931fdacSSumit Garg #define SQ_SYS_TIMCTL_BASE 0x2a810000 555931fdacSSumit Garg #define PLAT_SQ_NSTIMER_FRAME_ID 0 565931fdacSSumit Garg 57*cfe19f85SArd Biesheuvel #define DRAMINFO_BASE 0x2E00FFC0 58*cfe19f85SArd Biesheuvel 5905377100SSumit Garg #define PLAT_SQ_MHU_BASE 0x45000000 6005377100SSumit Garg 61b7ad0444SSumit Garg #define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000 62b7ad0444SSumit Garg #define SCPI_CMD_GET_DRAMINFO 0x1 63b7ad0444SSumit Garg 6485427debSSumit Garg #define SQ_BOOT_CFG_ADDR 0x45410000 6585427debSSumit Garg #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 6685427debSSumit Garg #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 6785427debSSumit Garg 68b529799fSSumit Garg #define PLAT_SQ_GICD_BASE 0x30000000 69b529799fSSumit Garg #define PLAT_SQ_GICR_BASE 0x30400000 70b529799fSSumit Garg 71c35d59a3SSumit Garg #endif /* __PLATFORM_DEF_H__ */ 72