1c35d59a3SSumit Garg /* 2c35d59a3SSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3c35d59a3SSumit Garg * 4c35d59a3SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5c35d59a3SSumit Garg */ 6c35d59a3SSumit Garg 7c35d59a3SSumit Garg #ifndef __PLATFORM_DEF_H__ 8c35d59a3SSumit Garg #define __PLATFORM_DEF_H__ 9c35d59a3SSumit Garg 10c35d59a3SSumit Garg #include <common_def.h> 11c35d59a3SSumit Garg 12c35d59a3SSumit Garg #define CACHE_WRITEBACK_SHIFT 6 13c35d59a3SSumit Garg #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 14c35d59a3SSumit Garg 15c35d59a3SSumit Garg #define PLATFORM_STACK_SIZE 0x400 16c35d59a3SSumit Garg 17c35d59a3SSumit Garg #define BL31_BASE 0x04000000 18c35d59a3SSumit Garg #define BL31_SIZE 0x00080000 19c35d59a3SSumit Garg #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 20c35d59a3SSumit Garg 21*67b40070SSumit Garg /* UART related constants */ 22*67b40070SSumit Garg #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 23*67b40070SSumit Garg #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 24*67b40070SSumit Garg #define SQ_CONSOLE_BAUDRATE 115200 25*67b40070SSumit Garg 2685427debSSumit Garg #define SQ_BOOT_CFG_ADDR 0x45410000 2785427debSSumit Garg #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 2885427debSSumit Garg #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 2985427debSSumit Garg 30c35d59a3SSumit Garg #endif /* __PLATFORM_DEF_H__ */ 31