1c35d59a3SSumit Garg /* 2c35d59a3SSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3c35d59a3SSumit Garg * 4c35d59a3SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5c35d59a3SSumit Garg */ 6c35d59a3SSumit Garg 7c35d59a3SSumit Garg #ifndef __PLATFORM_DEF_H__ 8c35d59a3SSumit Garg #define __PLATFORM_DEF_H__ 9c35d59a3SSumit Garg 10c35d59a3SSumit Garg #include <common_def.h> 11c35d59a3SSumit Garg 12007a7a33SSumit Garg /* CPU topology */ 13007a7a33SSumit Garg #define PLAT_MAX_CORES_PER_CLUSTER 2 14007a7a33SSumit Garg #define PLAT_CLUSTER_COUNT 12 15007a7a33SSumit Garg #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 16007a7a33SSumit Garg PLAT_MAX_CORES_PER_CLUSTER) 17007a7a33SSumit Garg 18c35d59a3SSumit Garg #define CACHE_WRITEBACK_SHIFT 6 19c35d59a3SSumit Garg #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 20c35d59a3SSumit Garg 21c35d59a3SSumit Garg #define PLATFORM_STACK_SIZE 0x400 22c35d59a3SSumit Garg 23c35d59a3SSumit Garg #define BL31_BASE 0x04000000 24c35d59a3SSumit Garg #define BL31_SIZE 0x00080000 25c35d59a3SSumit Garg #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 26c35d59a3SSumit Garg 270eb275c9SSumit Garg #define PLAT_SQ_CCN_BASE 0x32000000 280eb275c9SSumit Garg #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 290eb275c9SSumit Garg 0, /* Cluster 0 */ \ 300eb275c9SSumit Garg 18, /* Cluster 1 */ \ 310eb275c9SSumit Garg 11, /* Cluster 2 */ \ 320eb275c9SSumit Garg 29, /* Cluster 3 */ \ 330eb275c9SSumit Garg 35, /* Cluster 4 */ \ 340eb275c9SSumit Garg 17, /* Cluster 5 */ \ 350eb275c9SSumit Garg 12, /* Cluster 6 */ \ 360eb275c9SSumit Garg 30, /* Cluster 7 */ \ 370eb275c9SSumit Garg 14, /* Cluster 8 */ \ 380eb275c9SSumit Garg 32, /* Cluster 9 */ \ 390eb275c9SSumit Garg 15, /* Cluster 10 */ \ 400eb275c9SSumit Garg 33 /* Cluster 11 */ 410eb275c9SSumit Garg 4267b40070SSumit Garg /* UART related constants */ 4367b40070SSumit Garg #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 4467b40070SSumit Garg #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 4567b40070SSumit Garg #define SQ_CONSOLE_BAUDRATE 115200 4667b40070SSumit Garg 47*5931fdacSSumit Garg #define SQ_SYS_CNTCTL_BASE 0x2a430000 48*5931fdacSSumit Garg 49*5931fdacSSumit Garg #define SQ_SYS_TIMCTL_BASE 0x2a810000 50*5931fdacSSumit Garg #define PLAT_SQ_NSTIMER_FRAME_ID 0 51*5931fdacSSumit Garg 5285427debSSumit Garg #define SQ_BOOT_CFG_ADDR 0x45410000 5385427debSSumit Garg #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 5485427debSSumit Garg #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 5585427debSSumit Garg 56b529799fSSumit Garg #define PLAT_SQ_GICD_BASE 0x30000000 57b529799fSSumit Garg #define PLAT_SQ_GICR_BASE 0x30400000 58b529799fSSumit Garg 59c35d59a3SSumit Garg #endif /* __PLATFORM_DEF_H__ */ 60