1c35d59a3SSumit Garg /* 2c35d59a3SSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3c35d59a3SSumit Garg * 4c35d59a3SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5c35d59a3SSumit Garg */ 6c35d59a3SSumit Garg 7c35d59a3SSumit Garg #ifndef __PLATFORM_DEF_H__ 8c35d59a3SSumit Garg #define __PLATFORM_DEF_H__ 9c35d59a3SSumit Garg 10c35d59a3SSumit Garg #include <common_def.h> 11c35d59a3SSumit Garg 12*007a7a33SSumit Garg /* CPU topology */ 13*007a7a33SSumit Garg #define PLAT_MAX_CORES_PER_CLUSTER 2 14*007a7a33SSumit Garg #define PLAT_CLUSTER_COUNT 12 15*007a7a33SSumit Garg #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 16*007a7a33SSumit Garg PLAT_MAX_CORES_PER_CLUSTER) 17*007a7a33SSumit Garg 18c35d59a3SSumit Garg #define CACHE_WRITEBACK_SHIFT 6 19c35d59a3SSumit Garg #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 20c35d59a3SSumit Garg 21c35d59a3SSumit Garg #define PLATFORM_STACK_SIZE 0x400 22c35d59a3SSumit Garg 23c35d59a3SSumit Garg #define BL31_BASE 0x04000000 24c35d59a3SSumit Garg #define BL31_SIZE 0x00080000 25c35d59a3SSumit Garg #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 26c35d59a3SSumit Garg 2767b40070SSumit Garg /* UART related constants */ 2867b40070SSumit Garg #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 2967b40070SSumit Garg #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 3067b40070SSumit Garg #define SQ_CONSOLE_BAUDRATE 115200 3167b40070SSumit Garg 3285427debSSumit Garg #define SQ_BOOT_CFG_ADDR 0x45410000 3385427debSSumit Garg #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 3485427debSSumit Garg #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 3585427debSSumit Garg 36c35d59a3SSumit Garg #endif /* __PLATFORM_DEF_H__ */ 37