1434454a2SArd Biesheuvel/* 2*91e6bef9SMadhukar Pappireddy * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3434454a2SArd Biesheuvel * 4434454a2SArd Biesheuvel * SPDX-License-Identifier: BSD-3-Clause 5434454a2SArd Biesheuvel */ 6434454a2SArd Biesheuvel 7434454a2SArd Biesheuvel#ifndef SYNQUACER_PLAT_LD_S__ 8434454a2SArd Biesheuvel#define SYNQUACER_PLAT_LD_S__ 9434454a2SArd Biesheuvel 10*91e6bef9SMadhukar Pappireddy#include <lib/xlat_tables/xlat_tables_defs.h> 11434454a2SArd Biesheuvel 12434454a2SArd Biesheuvel#define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM 13434454a2SArd Biesheuvel 14434454a2SArd BiesheuvelMEMORY { 15434454a2SArd Biesheuvel SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE 16434454a2SArd Biesheuvel} 17434454a2SArd Biesheuvel 18434454a2SArd BiesheuvelSECTIONS 19434454a2SArd Biesheuvel{ 20434454a2SArd Biesheuvel /* 21434454a2SArd Biesheuvel * Put the page tables in secure DRAM so that the PTW can make cacheable 22434454a2SArd Biesheuvel * accesses, as the core SPM code expects. (The SRAM on SynQuacer does 23434454a2SArd Biesheuvel * not support inner shareable WBWA mappings so it is mapped normal 24434454a2SArd Biesheuvel * non-cacheable) 25434454a2SArd Biesheuvel */ 26434454a2SArd Biesheuvel sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) { 27434454a2SArd Biesheuvel *(sp_xlat_table) 28434454a2SArd Biesheuvel *(.bss.sp_base_xlat_table) 29434454a2SArd Biesheuvel } >SP_DRAM 30434454a2SArd Biesheuvel} 31434454a2SArd Biesheuvel 32434454a2SArd Biesheuvel#endif /* SYNQUACER_PLAT_LD_S__ */ 33