1*434454a2SArd Biesheuvel/* 2*434454a2SArd Biesheuvel * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*434454a2SArd Biesheuvel * 4*434454a2SArd Biesheuvel * SPDX-License-Identifier: BSD-3-Clause 5*434454a2SArd Biesheuvel */ 6*434454a2SArd Biesheuvel 7*434454a2SArd Biesheuvel#ifndef SYNQUACER_PLAT_LD_S__ 8*434454a2SArd Biesheuvel#define SYNQUACER_PLAT_LD_S__ 9*434454a2SArd Biesheuvel 10*434454a2SArd Biesheuvel#include <xlat_tables_defs.h> 11*434454a2SArd Biesheuvel 12*434454a2SArd Biesheuvel#define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM 13*434454a2SArd Biesheuvel 14*434454a2SArd BiesheuvelMEMORY { 15*434454a2SArd Biesheuvel SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE 16*434454a2SArd Biesheuvel} 17*434454a2SArd Biesheuvel 18*434454a2SArd BiesheuvelSECTIONS 19*434454a2SArd Biesheuvel{ 20*434454a2SArd Biesheuvel /* 21*434454a2SArd Biesheuvel * Put the page tables in secure DRAM so that the PTW can make cacheable 22*434454a2SArd Biesheuvel * accesses, as the core SPM code expects. (The SRAM on SynQuacer does 23*434454a2SArd Biesheuvel * not support inner shareable WBWA mappings so it is mapped normal 24*434454a2SArd Biesheuvel * non-cacheable) 25*434454a2SArd Biesheuvel */ 26*434454a2SArd Biesheuvel sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) { 27*434454a2SArd Biesheuvel *(sp_xlat_table) 28*434454a2SArd Biesheuvel *(.bss.sp_base_xlat_table) 29*434454a2SArd Biesheuvel } >SP_DRAM 30*434454a2SArd Biesheuvel} 31*434454a2SArd Biesheuvel 32*434454a2SArd Biesheuvel#endif /* SYNQUACER_PLAT_LD_S__ */ 33