1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/arm/css/css_mhu_doorbell.h> 13 #include <drivers/arm/css/css_scp.h> 14 #include <drivers/arm/css/scmi.h> 15 #include <plat/arm/css/common/css_pm.h> 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 #include <scmi_sq.h> 20 #include <sq_common.h> 21 22 /* 23 * This file implements the SCP helper functions using SCMI protocol. 24 */ 25 26 DEFINE_BAKERY_LOCK(sq_scmi_lock); 27 #define SQ_SCMI_LOCK_GET_INSTANCE (&sq_scmi_lock) 28 29 #define SQ_SCMI_PAYLOAD_BASE PLAT_SQ_SCP_COM_SHARED_MEM_BASE 30 #define MHU_CPU_INTR_S_SET_OFFSET 0x308 31 32 const uint32_t sq_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = { 33 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 34 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 35 }; 36 37 static scmi_channel_plat_info_t sq_scmi_plat_info = { 38 .scmi_mbx_mem = SQ_SCMI_PAYLOAD_BASE, 39 .db_reg_addr = PLAT_SQ_MHU_BASE + MHU_CPU_INTR_S_SET_OFFSET, 40 .db_preserve_mask = 0xfffffffe, 41 .db_modify_mask = 0x1, 42 .ring_doorbell = &mhu_ring_doorbell, 43 }; 44 45 /* 46 * SCMI power state parameter bit field encoding for SynQuacer platform. 47 * 48 * 31 20 19 16 15 12 11 8 7 4 3 0 49 * +-------------------------------------------------------------+ 50 * | SBZ | Max level | Level 3 | Level 2 | Level 1 | Level 0 | 51 * | | | state | state | state | state | 52 * +-------------------------------------------------------------+ 53 * 54 * `Max level` encodes the highest level that has a valid power state 55 * encoded in the power state. 56 */ 57 #define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 16 58 #define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4 59 #define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \ 60 ((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1) 61 #define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level) \ 62 (_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\ 63 << SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT 64 #define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state) \ 65 (((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \ 66 & SCMI_PWR_STATE_MAX_PWR_LVL_MASK) 67 68 #define SCMI_PWR_STATE_LVL_WIDTH 4 69 #define SCMI_PWR_STATE_LVL_MASK \ 70 ((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1) 71 #define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state) \ 72 (_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK) \ 73 << (SCMI_PWR_STATE_LVL_WIDTH * (_level)) 74 #define SCMI_GET_PWR_STATE_LVL(_power_state, _level) \ 75 (((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) & \ 76 SCMI_PWR_STATE_LVL_MASK) 77 78 /* 79 * The SCMI power state enumeration for a power domain level 80 */ 81 typedef enum { 82 scmi_power_state_off = 0, 83 scmi_power_state_on = 1, 84 scmi_power_state_sleep = 2, 85 } scmi_power_state_t; 86 87 /* 88 * The global handle for invoking the SCMI driver APIs after the driver 89 * has been initialized. 90 */ 91 static void *sq_scmi_handle; 92 93 /* The SCMI channel global object */ 94 static scmi_channel_t channel; 95 96 /* 97 * Helper function to turn off a CPU power domain and 98 * its parent power domains if applicable. 99 */ 100 void sq_scmi_off(const struct psci_power_state *target_state) 101 { 102 int lvl = 0, ret; 103 uint32_t scmi_pwr_state = 0; 104 105 /* At-least the CPU level should be specified to be OFF */ 106 assert(target_state->pwr_domain_state[SQ_PWR_LVL0] == 107 SQ_LOCAL_STATE_OFF); 108 109 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 110 if (target_state->pwr_domain_state[lvl] == SQ_LOCAL_STATE_RUN) 111 break; 112 113 assert(target_state->pwr_domain_state[lvl] == 114 SQ_LOCAL_STATE_OFF); 115 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, 116 scmi_power_state_off); 117 } 118 119 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); 120 121 ret = scmi_pwr_state_set(sq_scmi_handle, 122 sq_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()], 123 scmi_pwr_state); 124 125 if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { 126 ERROR("SCMI set power state command return 0x%x unexpected\n", 127 ret); 128 panic(); 129 } 130 } 131 132 /* 133 * Helper function to turn ON a CPU power domain and 134 *its parent power domains if applicable. 135 */ 136 void sq_scmi_on(u_register_t mpidr) 137 { 138 int lvl = 0, ret, core_pos; 139 uint32_t scmi_pwr_state = 0; 140 141 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) 142 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl, 143 scmi_power_state_on); 144 145 SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1); 146 147 core_pos = plat_core_pos_by_mpidr(mpidr); 148 assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT); 149 150 ret = scmi_pwr_state_set(sq_scmi_handle, 151 sq_core_pos_to_scmi_dmn_id_map[core_pos], 152 scmi_pwr_state); 153 154 if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) { 155 ERROR("SCMI set power state command return 0x%x unexpected\n", 156 ret); 157 panic(); 158 } 159 } 160 161 void __dead2 sq_scmi_system_off(int state) 162 { 163 int ret; 164 165 /* 166 * Disable GIC CPU interface to prevent pending interrupt from waking 167 * up the AP from WFI. 168 */ 169 sq_gic_cpuif_disable(); 170 171 /* 172 * Issue SCMI command. First issue a graceful 173 * request and if that fails force the request. 174 */ 175 ret = scmi_sys_pwr_state_set(sq_scmi_handle, 176 SCMI_SYS_PWR_FORCEFUL_REQ, 177 state); 178 179 if (ret != SCMI_E_SUCCESS) { 180 ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n", 181 state, ret); 182 panic(); 183 } 184 wfi(); 185 ERROR("SCMI set power state: operation not handled.\n"); 186 panic(); 187 } 188 189 /* 190 * Helper function to reset the system via SCMI. 191 */ 192 void __dead2 sq_scmi_sys_shutdown(void) 193 { 194 sq_scmi_system_off(SCMI_SYS_PWR_SHUTDOWN); 195 } 196 197 void __dead2 sq_scmi_sys_reboot(void) 198 { 199 sq_scmi_system_off(SCMI_SYS_PWR_COLD_RESET); 200 } 201 202 static int scmi_ap_core_init(scmi_channel_t *ch) 203 { 204 #if PROGRAMMABLE_RESET_ADDRESS 205 uint32_t version; 206 int ret; 207 208 ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version); 209 if (ret != SCMI_E_SUCCESS) { 210 WARN("SCMI AP core protocol version message failed\n"); 211 return -1; 212 } 213 214 if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) { 215 WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n", 216 version, SCMI_AP_CORE_PROTO_VER); 217 return -1; 218 } 219 INFO("SCMI AP core protocol version 0x%x detected\n", version); 220 #endif 221 return 0; 222 } 223 224 void __init plat_sq_pwrc_setup(void) 225 { 226 channel.info = &sq_scmi_plat_info; 227 channel.lock = SQ_SCMI_LOCK_GET_INSTANCE; 228 sq_scmi_handle = scmi_init(&channel); 229 if (sq_scmi_handle == NULL) { 230 ERROR("SCMI Initialization failed\n"); 231 panic(); 232 } 233 if (scmi_ap_core_init(&channel) < 0) { 234 ERROR("SCMI AP core protocol initialization failed\n"); 235 panic(); 236 } 237 } 238 239 uint32_t sq_scmi_get_draminfo(struct draminfo *info) 240 { 241 scmi_get_draminfo(sq_scmi_handle, info); 242 243 return 0; 244 } 245