1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bakery_lock.h> 10 #include <mmio.h> 11 #include <platform_def.h> 12 #include <sq_common.h> 13 #include "sq_mhu.h" 14 15 /* SCP MHU secure channel registers */ 16 #define SCP_INTR_S_STAT 0x200 17 #define SCP_INTR_S_SET 0x208 18 #define SCP_INTR_S_CLEAR 0x210 19 20 /* CPU MHU secure channel registers */ 21 #define CPU_INTR_S_STAT 0x300 22 #define CPU_INTR_S_SET 0x308 23 #define CPU_INTR_S_CLEAR 0x310 24 25 DEFINE_BAKERY_LOCK(sq_lock); 26 27 /* 28 * Slot 31 is reserved because the MHU hardware uses this register bit to 29 * indicate a non-secure access attempt. The total number of available slots is 30 * therefore 31 [30:0]. 31 */ 32 #define MHU_MAX_SLOT_ID 30 33 34 void mhu_secure_message_start(unsigned int slot_id) 35 { 36 assert(slot_id <= MHU_MAX_SLOT_ID); 37 38 bakery_lock_get(&sq_lock); 39 40 /* Make sure any previous command has finished */ 41 while (mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) & 42 (1 << slot_id)) 43 ; 44 } 45 46 void mhu_secure_message_send(unsigned int slot_id) 47 { 48 assert(slot_id <= MHU_MAX_SLOT_ID); 49 assert(!(mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) & 50 (1 << slot_id))); 51 52 /* Send command to SCP */ 53 mmio_write_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); 54 } 55 56 uint32_t mhu_secure_message_wait(void) 57 { 58 uint32_t response; 59 60 /* Wait for response from SCP */ 61 while (!(response = mmio_read_32(PLAT_SQ_MHU_BASE + SCP_INTR_S_STAT))) 62 ; 63 64 return response; 65 } 66 67 void mhu_secure_message_end(unsigned int slot_id) 68 { 69 assert(slot_id <= MHU_MAX_SLOT_ID); 70 71 /* 72 * Clear any response we got by writing one in the relevant slot bit to 73 * the CLEAR register 74 */ 75 mmio_write_32(PLAT_SQ_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); 76 77 bakery_lock_release(&sq_lock); 78 } 79 80 void mhu_secure_init(void) 81 { 82 bakery_lock_init(&sq_lock); 83 84 /* 85 * The STAT register resets to zero. Ensure it is in the expected state, 86 * as a stale or garbage value would make us think it's a message we've 87 * already sent. 88 */ 89 assert(mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) == 0); 90 } 91 92 void plat_sq_pwrc_setup(void) 93 { 94 mhu_secure_init(); 95 } 96