1f5cb15b0SAndre Przywara# 2f5cb15b0SAndre Przywara# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3f5cb15b0SAndre Przywara# 4f5cb15b0SAndre Przywara# SPDX-License-Identifier: BSD-3-Clause 5f5cb15b0SAndre Przywara# 6f5cb15b0SAndre Przywara 7f5cb15b0SAndre Przywarainclude lib/libfdt/libfdt.mk 8f5cb15b0SAndre Przywarainclude lib/xlat_tables_v2/xlat_tables.mk 9f5cb15b0SAndre Przywara 10f5cb15b0SAndre PrzywaraPLAT_INCLUDES := -Iplat/rpi/common/include \ 11f5cb15b0SAndre Przywara -Iplat/rpi/rpi4/include 12f5cb15b0SAndre Przywara 13f5cb15b0SAndre PrzywaraPLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ 14f5cb15b0SAndre Przywara plat/rpi/common/rpi3_common.c \ 15f5cb15b0SAndre Przywara ${XLAT_TABLES_LIB_SRCS} 16f5cb15b0SAndre Przywara 17f5cb15b0SAndre PrzywaraBL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ 18f5cb15b0SAndre Przywara plat/rpi/rpi4/aarch64/plat_helpers.S \ 19c4597e13SAndre Przywara plat/rpi/rpi4/aarch64/armstub8_header.S \ 20f5cb15b0SAndre Przywara drivers/arm/gic/common/gic_common.c \ 21f5cb15b0SAndre Przywara drivers/arm/gic/v2/gicv2_helpers.c \ 22f5cb15b0SAndre Przywara drivers/arm/gic/v2/gicv2_main.c \ 23f5cb15b0SAndre Przywara plat/common/plat_gicv2.c \ 24f5cb15b0SAndre Przywara plat/rpi/rpi4/rpi4_bl31_setup.c \ 25f5cb15b0SAndre Przywara plat/rpi/common/rpi3_pm.c \ 26f5cb15b0SAndre Przywara plat/common/plat_psci_common.c \ 27f5cb15b0SAndre Przywara plat/rpi/common/rpi3_topology.c \ 28*f67fa69cSAndre Przywara common/fdt_fixup.c \ 29f5cb15b0SAndre Przywara ${LIBFDT_SRCS} 30f5cb15b0SAndre Przywara 31f5cb15b0SAndre Przywara# For now we only support BL31, using the kernel loaded by the GPU firmware. 32f5cb15b0SAndre PrzywaraRESET_TO_BL31 := 1 33f5cb15b0SAndre Przywara 34f5cb15b0SAndre Przywara# All CPUs enter armstub8.bin. 35f5cb15b0SAndre PrzywaraCOLD_BOOT_SINGLE_CPU := 0 36f5cb15b0SAndre Przywara 37f5cb15b0SAndre Przywara# Tune compiler for Cortex-A72 38f5cb15b0SAndre Przywaraifeq ($(notdir $(CC)),armclang) 39f5cb15b0SAndre Przywara TF_CFLAGS_aarch64 += -mcpu=cortex-a72 40f5cb15b0SAndre Przywaraelse ifneq ($(findstring clang,$(notdir $(CC))),) 41f5cb15b0SAndre Przywara TF_CFLAGS_aarch64 += -mcpu=cortex-a72 42f5cb15b0SAndre Przywaraelse 43f5cb15b0SAndre Przywara TF_CFLAGS_aarch64 += -mtune=cortex-a72 44f5cb15b0SAndre Przywaraendif 45f5cb15b0SAndre Przywara 46c4597e13SAndre Przywara# Add support for platform supplied linker script for BL31 build 47c4597e13SAndre Przywara$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 48f5cb15b0SAndre Przywara 49f5cb15b0SAndre Przywara# Enable all errata workarounds for Cortex-A72 50f5cb15b0SAndre PrzywaraERRATA_A72_859971 := 1 51f5cb15b0SAndre Przywara 52f5cb15b0SAndre PrzywaraWORKAROUND_CVE_2017_5715 := 1 53f5cb15b0SAndre Przywara 54f5cb15b0SAndre Przywara# Add new default target when compiling this platform 55f5cb15b0SAndre Przywaraall: bl31 56f5cb15b0SAndre Przywara 57f5cb15b0SAndre Przywara# Build config flags 58f5cb15b0SAndre Przywara# ------------------ 59f5cb15b0SAndre Przywara 60f5cb15b0SAndre Przywara# Disable stack protector by default 61f5cb15b0SAndre PrzywaraENABLE_STACK_PROTECTOR := 0 62f5cb15b0SAndre Przywara 63f5cb15b0SAndre Przywara# Have different sections for code and rodata 64f5cb15b0SAndre PrzywaraSEPARATE_CODE_AND_RODATA := 1 65f5cb15b0SAndre Przywara 66f5cb15b0SAndre Przywara# Use Coherent memory 67f5cb15b0SAndre PrzywaraUSE_COHERENT_MEM := 1 68f5cb15b0SAndre Przywara 69f5cb15b0SAndre Przywara# Platform build flags 70f5cb15b0SAndre Przywara# -------------------- 71f5cb15b0SAndre Przywara 72448fb352SAndre Przywara# There is not much else than a Linux kernel to load at the moment. 73448fb352SAndre PrzywaraRPI3_DIRECT_LINUX_BOOT := 1 74f5cb15b0SAndre Przywara 75f5cb15b0SAndre Przywara# BL33 images are in AArch64 by default 76f5cb15b0SAndre PrzywaraRPI3_BL33_IN_AARCH32 := 0 77f5cb15b0SAndre Przywara 78f5cb15b0SAndre Przywara# UART to use at runtime. -1 means the runtime UART is disabled. 79f5cb15b0SAndre Przywara# Any other value means the default UART will be used. 80f5cb15b0SAndre PrzywaraRPI3_RUNTIME_UART := 0 81f5cb15b0SAndre Przywara 82f5cb15b0SAndre Przywara# Use normal memory mapping for ROM, FIP, SRAM and DRAM 83f5cb15b0SAndre PrzywaraRPI3_USE_UEFI_MAP := 0 84f5cb15b0SAndre Przywara 85f5cb15b0SAndre Przywara# Process platform flags 86f5cb15b0SAndre Przywara# ---------------------- 87f5cb15b0SAndre Przywara 88f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_BL33_IN_AARCH32)) 89f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT)) 90f5cb15b0SAndre Przywaraifdef RPI3_PRELOADED_DTB_BASE 91f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) 92f5cb15b0SAndre Przywaraendif 93f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_RUNTIME_UART)) 94f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_USE_UEFI_MAP)) 95f5cb15b0SAndre Przywara 96f5cb15b0SAndre Przywaraifeq (${ARCH},aarch32) 97f5cb15b0SAndre Przywara $(error Error: AArch32 not supported on rpi4) 98f5cb15b0SAndre Przywaraendif 99f5cb15b0SAndre Przywara 100f5cb15b0SAndre Przywaraifneq ($(ENABLE_STACK_PROTECTOR), 0) 101f5cb15b0SAndre PrzywaraPLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ 102f5cb15b0SAndre Przywara plat/rpi/common/rpi3_stack_protector.c 103f5cb15b0SAndre Przywaraendif 104