1*f5cb15b0SAndre Przywara# 2*f5cb15b0SAndre Przywara# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3*f5cb15b0SAndre Przywara# 4*f5cb15b0SAndre Przywara# SPDX-License-Identifier: BSD-3-Clause 5*f5cb15b0SAndre Przywara# 6*f5cb15b0SAndre Przywara 7*f5cb15b0SAndre Przywarainclude lib/libfdt/libfdt.mk 8*f5cb15b0SAndre Przywarainclude lib/xlat_tables_v2/xlat_tables.mk 9*f5cb15b0SAndre Przywara 10*f5cb15b0SAndre PrzywaraPLAT_INCLUDES := -Iplat/rpi/common/include \ 11*f5cb15b0SAndre Przywara -Iplat/rpi/rpi4/include 12*f5cb15b0SAndre Przywara 13*f5cb15b0SAndre PrzywaraPLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ 14*f5cb15b0SAndre Przywara plat/rpi/common/rpi3_common.c \ 15*f5cb15b0SAndre Przywara ${XLAT_TABLES_LIB_SRCS} 16*f5cb15b0SAndre Przywara 17*f5cb15b0SAndre PrzywaraBL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \ 18*f5cb15b0SAndre Przywara plat/rpi/rpi4/aarch64/plat_helpers.S \ 19*f5cb15b0SAndre Przywara drivers/arm/gic/common/gic_common.c \ 20*f5cb15b0SAndre Przywara drivers/arm/gic/v2/gicv2_helpers.c \ 21*f5cb15b0SAndre Przywara drivers/arm/gic/v2/gicv2_main.c \ 22*f5cb15b0SAndre Przywara plat/common/plat_gicv2.c \ 23*f5cb15b0SAndre Przywara plat/rpi/rpi4/rpi4_bl31_setup.c \ 24*f5cb15b0SAndre Przywara plat/rpi/common/rpi3_pm.c \ 25*f5cb15b0SAndre Przywara plat/common/plat_psci_common.c \ 26*f5cb15b0SAndre Przywara plat/rpi/common/rpi3_topology.c \ 27*f5cb15b0SAndre Przywara ${LIBFDT_SRCS} 28*f5cb15b0SAndre Przywara 29*f5cb15b0SAndre Przywara# For now we only support BL31, using the kernel loaded by the GPU firmware. 30*f5cb15b0SAndre PrzywaraRESET_TO_BL31 := 1 31*f5cb15b0SAndre Przywara 32*f5cb15b0SAndre Przywara# All CPUs enter armstub8.bin. 33*f5cb15b0SAndre PrzywaraCOLD_BOOT_SINGLE_CPU := 0 34*f5cb15b0SAndre Przywara 35*f5cb15b0SAndre Przywara# Tune compiler for Cortex-A72 36*f5cb15b0SAndre Przywaraifeq ($(notdir $(CC)),armclang) 37*f5cb15b0SAndre Przywara TF_CFLAGS_aarch64 += -mcpu=cortex-a72 38*f5cb15b0SAndre Przywaraelse ifneq ($(findstring clang,$(notdir $(CC))),) 39*f5cb15b0SAndre Przywara TF_CFLAGS_aarch64 += -mcpu=cortex-a72 40*f5cb15b0SAndre Przywaraelse 41*f5cb15b0SAndre Przywara TF_CFLAGS_aarch64 += -mtune=cortex-a72 42*f5cb15b0SAndre Przywaraendif 43*f5cb15b0SAndre Przywara 44*f5cb15b0SAndre Przywara 45*f5cb15b0SAndre Przywara# Enable all errata workarounds for Cortex-A72 46*f5cb15b0SAndre PrzywaraERRATA_A72_859971 := 1 47*f5cb15b0SAndre Przywara 48*f5cb15b0SAndre PrzywaraWORKAROUND_CVE_2017_5715 := 1 49*f5cb15b0SAndre Przywara 50*f5cb15b0SAndre Przywara# Add new default target when compiling this platform 51*f5cb15b0SAndre Przywaraall: bl31 52*f5cb15b0SAndre Przywara 53*f5cb15b0SAndre Przywara# Build config flags 54*f5cb15b0SAndre Przywara# ------------------ 55*f5cb15b0SAndre Przywara 56*f5cb15b0SAndre Przywara# Disable stack protector by default 57*f5cb15b0SAndre PrzywaraENABLE_STACK_PROTECTOR := 0 58*f5cb15b0SAndre Przywara 59*f5cb15b0SAndre Przywara# Have different sections for code and rodata 60*f5cb15b0SAndre PrzywaraSEPARATE_CODE_AND_RODATA := 1 61*f5cb15b0SAndre Przywara 62*f5cb15b0SAndre Przywara# Use Coherent memory 63*f5cb15b0SAndre PrzywaraUSE_COHERENT_MEM := 1 64*f5cb15b0SAndre Przywara 65*f5cb15b0SAndre Przywara# Platform build flags 66*f5cb15b0SAndre Przywara# -------------------- 67*f5cb15b0SAndre Przywara 68*f5cb15b0SAndre Przywara# Assume that BL33 isn't the Linux kernel by default 69*f5cb15b0SAndre PrzywaraRPI3_DIRECT_LINUX_BOOT := 0 70*f5cb15b0SAndre Przywara 71*f5cb15b0SAndre Przywara# BL33 images are in AArch64 by default 72*f5cb15b0SAndre PrzywaraRPI3_BL33_IN_AARCH32 := 0 73*f5cb15b0SAndre Przywara 74*f5cb15b0SAndre Przywara# UART to use at runtime. -1 means the runtime UART is disabled. 75*f5cb15b0SAndre Przywara# Any other value means the default UART will be used. 76*f5cb15b0SAndre PrzywaraRPI3_RUNTIME_UART := 0 77*f5cb15b0SAndre Przywara 78*f5cb15b0SAndre Przywara# Use normal memory mapping for ROM, FIP, SRAM and DRAM 79*f5cb15b0SAndre PrzywaraRPI3_USE_UEFI_MAP := 0 80*f5cb15b0SAndre Przywara 81*f5cb15b0SAndre Przywara# Process platform flags 82*f5cb15b0SAndre Przywara# ---------------------- 83*f5cb15b0SAndre Przywara 84*f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_BL33_IN_AARCH32)) 85*f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT)) 86*f5cb15b0SAndre Przywaraifdef RPI3_PRELOADED_DTB_BASE 87*f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE)) 88*f5cb15b0SAndre Przywaraendif 89*f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_RUNTIME_UART)) 90*f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_USE_UEFI_MAP)) 91*f5cb15b0SAndre Przywara 92*f5cb15b0SAndre Przywara# Verify build config 93*f5cb15b0SAndre Przywara# ------------------- 94*f5cb15b0SAndre Przywara# 95*f5cb15b0SAndre Przywaraifneq (${RPI3_DIRECT_LINUX_BOOT}, 0) 96*f5cb15b0SAndre Przywara ifndef RPI3_PRELOADED_DTB_BASE 97*f5cb15b0SAndre Przywara $(error Error: RPI3_PRELOADED_DTB_BASE needed if RPI3_DIRECT_LINUX_BOOT=1) 98*f5cb15b0SAndre Przywara endif 99*f5cb15b0SAndre Przywaraendif 100*f5cb15b0SAndre Przywara 101*f5cb15b0SAndre Przywaraifeq (${ARCH},aarch32) 102*f5cb15b0SAndre Przywara $(error Error: AArch32 not supported on rpi4) 103*f5cb15b0SAndre Przywaraendif 104*f5cb15b0SAndre Przywara 105*f5cb15b0SAndre Przywaraifneq ($(ENABLE_STACK_PROTECTOR), 0) 106*f5cb15b0SAndre PrzywaraPLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ 107*f5cb15b0SAndre Przywara plat/rpi/common/rpi3_stack_protector.c 108*f5cb15b0SAndre Przywaraendif 109