xref: /rk3399_ARM-atf/plat/rpi/rpi4/platform.mk (revision bded41d9e49065f831b8f968cc646f5b860a23f8)
1f5cb15b0SAndre Przywara#
2*5be66449SBoyan Karatotev# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
3f5cb15b0SAndre Przywara#
4f5cb15b0SAndre Przywara# SPDX-License-Identifier: BSD-3-Clause
5f5cb15b0SAndre Przywara#
6f5cb15b0SAndre Przywara
7f5cb15b0SAndre Przywarainclude lib/libfdt/libfdt.mk
8f5cb15b0SAndre Przywarainclude lib/xlat_tables_v2/xlat_tables.mk
9f5cb15b0SAndre Przywara
10830c7657SJan Kiszkainclude drivers/arm/gic/v2/gicv2.mk
11830c7657SJan Kiszka
12f5cb15b0SAndre PrzywaraPLAT_INCLUDES		:=	-Iplat/rpi/common/include		\
13f5cb15b0SAndre Przywara				-Iplat/rpi/rpi4/include
14f5cb15b0SAndre Przywara
15f5cb15b0SAndre PrzywaraPLAT_BL_COMMON_SOURCES	:=	drivers/ti/uart/aarch64/16550_console.S	\
165e6d821cSAndre Przywara				drivers/arm/pl011/aarch64/pl011_console.S \
17f5cb15b0SAndre Przywara				plat/rpi/common/rpi3_common.c		\
18b5029782SMario Bălănică				plat/rpi/common/rpi3_console_dual.c	\
19f5cb15b0SAndre Przywara				${XLAT_TABLES_LIB_SRCS}
20f5cb15b0SAndre Przywara
21f5cb15b0SAndre PrzywaraBL31_SOURCES		+=	lib/cpus/aarch64/cortex_a72.S		\
2207aa0c7eSAndre Przywara				plat/rpi/common/aarch64/plat_helpers.S	\
2397ef5305SMario Bălănică				plat/rpi/common/aarch64/armstub8_header.S \
249cc3fa1bSAndre Przywara				drivers/delay_timer/delay_timer.c	\
259cc3fa1bSAndre Przywara				drivers/gpio/gpio.c			\
269cc3fa1bSAndre Przywara				drivers/rpi3/gpio/rpi3_gpio.c		\
27f5cb15b0SAndre Przywara				plat/common/plat_gicv2.c                \
2897ef5305SMario Bălănică				plat/rpi/common/rpi4_bl31_setup.c	\
2997ef5305SMario Bălănică				plat/rpi/rpi4/rpi4_setup.c		\
30f5cb15b0SAndre Przywara				plat/rpi/common/rpi3_pm.c		\
31f5cb15b0SAndre Przywara				plat/common/plat_psci_common.c		\
32f5cb15b0SAndre Przywara				plat/rpi/common/rpi3_topology.c		\
33f67fa69cSAndre Przywara				common/fdt_fixup.c			\
3442488064SAndre Przywara				common/fdt_wrappers.c			\
35830c7657SJan Kiszka				${LIBFDT_SRCS}				\
36830c7657SJan Kiszka				${GICV2_SOURCES}
37f5cb15b0SAndre Przywara
38f5cb15b0SAndre Przywara# For now we only support BL31, using the kernel loaded by the GPU firmware.
39f5cb15b0SAndre PrzywaraRESET_TO_BL31		:=	1
40f5cb15b0SAndre Przywara
41f5cb15b0SAndre Przywara# All CPUs enter armstub8.bin.
42f5cb15b0SAndre PrzywaraCOLD_BOOT_SINGLE_CPU	:=	0
43f5cb15b0SAndre Przywara
44f5cb15b0SAndre Przywara# Tune compiler for Cortex-A72
458620bd0bSChris Kayifeq ($($(ARCH)-cc-id),arm-clang)
46f5cb15b0SAndre Przywara    TF_CFLAGS_aarch64	+=	-mcpu=cortex-a72
478620bd0bSChris Kayelse ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
48f5cb15b0SAndre Przywara    TF_CFLAGS_aarch64	+=	-mcpu=cortex-a72
49f5cb15b0SAndre Przywaraelse
50f5cb15b0SAndre Przywara    TF_CFLAGS_aarch64	+=	-mtune=cortex-a72
51f5cb15b0SAndre Przywaraendif
52f5cb15b0SAndre Przywara
53c4597e13SAndre Przywara# Add support for platform supplied linker script for BL31 build
54*5be66449SBoyan KaratotevPLAT_EXTRA_LD_SCRIPT	:=	1
55f5cb15b0SAndre Przywara
56f5cb15b0SAndre Przywara# Enable all errata workarounds for Cortex-A72
57f5cb15b0SAndre PrzywaraERRATA_A72_859971		:= 1
58f5cb15b0SAndre Przywara
59f5cb15b0SAndre PrzywaraWORKAROUND_CVE_2017_5715	:= 1
60f5cb15b0SAndre Przywara
61f5cb15b0SAndre Przywara# Add new default target when compiling this platform
62f5cb15b0SAndre Przywaraall: bl31
63f5cb15b0SAndre Przywara
64f5cb15b0SAndre Przywara# Build config flags
65f5cb15b0SAndre Przywara# ------------------
66f5cb15b0SAndre Przywara
67f5cb15b0SAndre Przywara# Disable stack protector by default
68f5cb15b0SAndre PrzywaraENABLE_STACK_PROTECTOR	 	:= 0
69f5cb15b0SAndre Przywara
70f5cb15b0SAndre Przywara# Have different sections for code and rodata
71f5cb15b0SAndre PrzywaraSEPARATE_CODE_AND_RODATA	:= 1
72f5cb15b0SAndre Przywara
73f5cb15b0SAndre Przywara# Use Coherent memory
74f5cb15b0SAndre PrzywaraUSE_COHERENT_MEM		:= 1
75f5cb15b0SAndre Przywara
76f5cb15b0SAndre Przywara# Platform build flags
77f5cb15b0SAndre Przywara# --------------------
78f5cb15b0SAndre Przywara
79448fb352SAndre Przywara# There is not much else than a Linux kernel to load at the moment.
80448fb352SAndre PrzywaraRPI3_DIRECT_LINUX_BOOT		:= 1
81f5cb15b0SAndre Przywara
82f5cb15b0SAndre Przywara# BL33 images are in AArch64 by default
83f5cb15b0SAndre PrzywaraRPI3_BL33_IN_AARCH32		:= 0
84f5cb15b0SAndre Przywara
85f5cb15b0SAndre Przywara# UART to use at runtime. -1 means the runtime UART is disabled.
86f5cb15b0SAndre Przywara# Any other value means the default UART will be used.
87f5cb15b0SAndre PrzywaraRPI3_RUNTIME_UART		:= 0
88f5cb15b0SAndre Przywara
89f5cb15b0SAndre Przywara# Use normal memory mapping for ROM, FIP, SRAM and DRAM
90f5cb15b0SAndre PrzywaraRPI3_USE_UEFI_MAP		:= 0
91f5cb15b0SAndre Przywara
926e63cdc5SJeremy Linton# SMCCC PCI support (should be enabled for ACPI builds)
936e63cdc5SJeremy LintonSMC_PCI_SUPPORT            	:= 0
946e63cdc5SJeremy Linton
95f5cb15b0SAndre Przywara# Process platform flags
96f5cb15b0SAndre Przywara# ----------------------
97f5cb15b0SAndre Przywara
98f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_BL33_IN_AARCH32))
99f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT))
100f5cb15b0SAndre Przywaraifdef RPI3_PRELOADED_DTB_BASE
101f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE))
102f5cb15b0SAndre Przywaraendif
103f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_RUNTIME_UART))
104f5cb15b0SAndre Przywara$(eval $(call add_define,RPI3_USE_UEFI_MAP))
1056e63cdc5SJeremy Linton$(eval $(call add_define,SMC_PCI_SUPPORT))
106f5cb15b0SAndre Przywara
107f5cb15b0SAndre Przywaraifeq (${ARCH},aarch32)
108f5cb15b0SAndre Przywara  $(error Error: AArch32 not supported on rpi4)
109f5cb15b0SAndre Przywaraendif
110f5cb15b0SAndre Przywara
111f5cb15b0SAndre Przywaraifneq ($(ENABLE_STACK_PROTECTOR), 0)
112f5cb15b0SAndre PrzywaraPLAT_BL_COMMON_SOURCES	+=	drivers/rpi3/rng/rpi3_rng.c		\
113f5cb15b0SAndre Przywara				plat/rpi/common/rpi3_stack_protector.c
114f5cb15b0SAndre Przywaraendif
1156e63cdc5SJeremy Linton
1166e63cdc5SJeremy Lintonifeq ($(SMC_PCI_SUPPORT), 1)
117682607fbSMario BălănicăBL31_SOURCES            +=      plat/rpi/common/rpi_pci_svc.c
1186e63cdc5SJeremy Lintonendif
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