1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "rpi_hw.h" 16 17 /* Special value used to verify platform parameters from BL2 to BL31 */ 18 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) 19 20 #define PLATFORM_STACK_SIZE ULL(0x1000) 21 22 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 23 #define PLATFORM_CLUSTER_COUNT U(1) 24 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 25 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT 26 27 #define RPI4_PRIMARY_CPU U(0) 28 29 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 30 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 31 PLATFORM_CORE_COUNT) 32 33 #define PLAT_MAX_RET_STATE U(1) 34 #define PLAT_MAX_OFF_STATE U(2) 35 36 /* Local power state for power domains in Run state. */ 37 #define PLAT_LOCAL_STATE_RUN U(0) 38 /* Local power state for retention. Valid only for CPU power domains */ 39 #define PLAT_LOCAL_STATE_RET U(1) 40 /* 41 * Local power state for OFF/power-down. Valid for CPU and cluster power 42 * domains. 43 */ 44 #define PLAT_LOCAL_STATE_OFF U(2) 45 46 /* 47 * Macros used to parse state information from State-ID if it is using the 48 * recommended encoding for State-ID. 49 */ 50 #define PLAT_LOCAL_PSTATE_WIDTH U(4) 51 #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) 52 53 /* 54 * Some data must be aligned on the biggest cache line size in the platform. 55 * This is known only to the platform as it might have a combination of 56 * integrated and external caches. 57 */ 58 #define CACHE_WRITEBACK_SHIFT U(6) 59 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 60 61 /* 62 * I/O registers. 63 */ 64 #define DEVICE0_BASE RPI_IO_BASE 65 #define DEVICE0_SIZE RPI_IO_SIZE 66 67 /* 68 * Mailbox to control the secondary cores. All secondary cores are held in a 69 * wait loop in cold boot. To release them perform the following steps (plus 70 * any additional barriers that may be needed): 71 * 72 * uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT; 73 * *entrypoint = ADDRESS_TO_JUMP_TO; 74 * 75 * uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; 76 * mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO; 77 * 78 * sev(); 79 */ 80 /* The secure entry point to be used on warm reset by all CPUs. */ 81 #define PLAT_RPI3_TM_ENTRYPOINT 0x100 82 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8) 83 84 /* Hold entries for each CPU. */ 85 #define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \ 86 PLAT_RPI3_TM_ENTRYPOINT_SIZE) 87 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8) 88 #define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \ 89 PLATFORM_CORE_COUNT) 90 91 #define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \ 92 PLAT_RPI3_TM_HOLD_SIZE) 93 94 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0) 95 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1) 96 97 /* 98 * BL31 specific defines. 99 * 100 * Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the 101 * current BL31 debug size plus a little space for growth. 102 */ 103 #define PLAT_MAX_BL31_SIZE ULL(0x80000) 104 105 #define BL31_BASE ULL(0x1000) 106 #define BL31_LIMIT ULL(0x80000) 107 #define BL31_PROGBITS_LIMIT ULL(0x80000) 108 109 #define SEC_SRAM_ID 0 110 #define SEC_DRAM_ID 1 111 112 /* 113 * Other memory-related defines. 114 */ 115 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 116 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 117 118 #define MAX_MMAP_REGIONS 8 119 #define MAX_XLAT_TABLES 4 120 121 #define MAX_IO_DEVICES U(3) 122 #define MAX_IO_HANDLES U(4) 123 124 #define MAX_IO_BLOCK_DEVICES U(1) 125 126 /* 127 * Serial-related constants. 128 */ 129 #define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE 130 #define PLAT_RPI3_UART_BAUDRATE ULL(115200) 131 132 /* 133 * System counter 134 */ 135 #define SYS_COUNTER_FREQ_IN_TICKS ULL(54000000) 136 137 #endif /* PLATFORM_DEF_H */ 138