1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <lib/optee_utils.h> 16 #include <lib/xlat_tables/xlat_mmu_helpers.h> 17 #include <lib/xlat_tables/xlat_tables_defs.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/rpi3/gpio/rpi3_gpio.h> 20 #include <drivers/rpi3/sdhost/rpi3_sdhost.h> 21 22 #include <rpi_shared.h> 23 24 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 26 27 /* Data structure which holds the MMC info */ 28 static struct mmc_device_info mmc_info; 29 30 static void rpi3_sdhost_setup(void) 31 { 32 struct rpi3_sdhost_params params; 33 34 memset(¶ms, 0, sizeof(struct rpi3_sdhost_params)); 35 params.reg_base = RPI3_SDHOST_BASE; 36 params.bus_width = MMC_BUS_WIDTH_1; 37 params.clk_rate = 50000000; 38 params.clk_rate_initial = (RPI3_SDHOST_MAX_CLOCK / HC_CLOCKDIVISOR_MAXVAL); 39 mmc_info.mmc_dev_type = MMC_IS_SD_HC; 40 mmc_info.ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 41 rpi3_sdhost_init(¶ms, &mmc_info); 42 } 43 44 /******************************************************************************* 45 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 46 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 47 * Copy it to a safe location before its reclaimed by later BL2 functionality. 48 ******************************************************************************/ 49 50 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, 51 u_register_t arg2, u_register_t arg3) 52 { 53 meminfo_t *mem_layout = (meminfo_t *) arg1; 54 55 /* Initialize the console to provide early debug support */ 56 rpi3_console_init(); 57 58 /* Enable arch timer */ 59 generic_delay_timer_init(); 60 61 /* Setup GPIO driver */ 62 rpi3_gpio_init(); 63 64 /* Setup the BL2 memory layout */ 65 bl2_tzram_layout = *mem_layout; 66 67 /* Setup SDHost driver */ 68 rpi3_sdhost_setup(); 69 70 plat_rpi3_io_setup(); 71 } 72 73 void bl2_platform_setup(void) 74 { 75 /* 76 * This is where a TrustZone address space controller and other 77 * security related peripherals would be configured. 78 */ 79 } 80 81 /******************************************************************************* 82 * Perform the very early platform specific architectural setup here. 83 ******************************************************************************/ 84 void bl2_plat_arch_setup(void) 85 { 86 rpi3_setup_page_tables(bl2_tzram_layout.total_base, 87 bl2_tzram_layout.total_size, 88 BL_CODE_BASE, BL_CODE_END, 89 BL_RO_DATA_BASE, BL_RO_DATA_END 90 #if USE_COHERENT_MEM 91 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END 92 #endif 93 ); 94 95 enable_mmu_el1(0); 96 } 97 98 /******************************************************************************* 99 * This function can be used by the platforms to update/use image 100 * information for given `image_id`. 101 ******************************************************************************/ 102 int bl2_plat_handle_post_image_load(unsigned int image_id) 103 { 104 int err = 0; 105 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 106 #ifdef SPD_opteed 107 bl_mem_params_node_t *pager_mem_params = NULL; 108 bl_mem_params_node_t *paged_mem_params = NULL; 109 #endif 110 111 assert(bl_mem_params != NULL); 112 113 switch (image_id) { 114 case BL32_IMAGE_ID: 115 #ifdef SPD_opteed 116 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 117 assert(pager_mem_params); 118 119 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 120 assert(paged_mem_params); 121 122 err = parse_optee_header(&bl_mem_params->ep_info, 123 &pager_mem_params->image_info, 124 &paged_mem_params->image_info); 125 if (err != 0) 126 WARN("OPTEE header parse error.\n"); 127 #endif 128 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry(); 129 break; 130 131 case BL33_IMAGE_ID: 132 /* BL33 expects to receive the primary CPU MPID (through r0) */ 133 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 134 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry(); 135 136 /* Shutting down the SDHost driver to let BL33 drives SDHost.*/ 137 rpi3_sdhost_stop(); 138 break; 139 140 default: 141 /* Do nothing in default case */ 142 break; 143 } 144 145 return err; 146 } 147