1 /* 2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_mmu_helpers.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <plat/common/platform.h> 18 19 #include <rpi_shared.h> 20 21 /* Data structure which holds the extents of the trusted SRAM for BL1 */ 22 static meminfo_t bl1_tzram_layout; 23 24 meminfo_t *bl1_plat_sec_mem_layout(void) 25 { 26 return &bl1_tzram_layout; 27 } 28 29 /******************************************************************************* 30 * Perform any BL1 specific platform actions. 31 ******************************************************************************/ 32 void bl1_early_platform_setup(void) 33 { 34 /* use the 19.2 MHz clock for the architected timer */ 35 mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_CONTROL_OFFSET, 0); 36 mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_PRESCALER_OFFSET, 37 0x80000000); 38 39 /* Initialize the console to provide early debug support */ 40 rpi3_console_init(); 41 42 /* 43 * Write the System Timer Frequency to CNTFRQ manually, this 44 * is required to use the delay_timer functionality. 45 */ 46 write_cntfrq_el0(plat_get_syscnt_freq2()); 47 48 /* Enable arch timer */ 49 generic_delay_timer_init(); 50 51 /* Allow BL1 to see the whole Trusted RAM */ 52 bl1_tzram_layout.total_base = BL_RAM_BASE; 53 bl1_tzram_layout.total_size = BL_RAM_SIZE; 54 } 55 56 /****************************************************************************** 57 * Perform the very early platform specific architecture setup. This only 58 * does basic initialization. Later architectural setup (bl1_arch_setup()) 59 * does not do anything platform specific. 60 *****************************************************************************/ 61 void bl1_plat_arch_setup(void) 62 { 63 rpi3_setup_page_tables(bl1_tzram_layout.total_base, 64 bl1_tzram_layout.total_size, 65 BL_CODE_BASE, BL1_CODE_END, 66 BL1_RO_DATA_BASE, BL1_RO_DATA_END 67 #if USE_COHERENT_MEM 68 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END 69 #endif 70 ); 71 72 enable_mmu_el3(0); 73 } 74 75 void bl1_platform_setup(void) 76 { 77 uint32_t __unused rev; 78 int __unused rc; 79 80 rc = rpi3_vc_hardware_get_board_revision(&rev); 81 82 if (rc == 0) { 83 const char __unused *model, __unused *info; 84 85 switch (rev) { 86 case 0xA02082: 87 model = "Raspberry Pi 3 Model B"; 88 info = "(1GB, Sony, UK)"; 89 break; 90 case 0xA22082: 91 model = "Raspberry Pi 3 Model B"; 92 info = "(1GB, Embest, China)"; 93 break; 94 case 0xA020D3: 95 model = "Raspberry Pi 3 Model B+"; 96 info = "(1GB, Sony, UK)"; 97 break; 98 default: 99 model = "Unknown"; 100 info = "(Unknown)"; 101 ERROR("rpi3: Unknown board revision 0x%08x\n", rev); 102 break; 103 } 104 105 NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev); 106 } else { 107 ERROR("rpi3: Unable to detect board revision\n"); 108 } 109 110 /* Initialise the IO layer and register platform IO devices */ 111 plat_rpi3_io_setup(); 112 } 113