1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 #include <plat/common/platform.h> 17 18 #include <rpi_hw.h> 19 20 #ifdef RPI_HAVE_GIC 21 #include <drivers/arm/gicv2.h> 22 #endif 23 24 /* Registers on top of RPI3_PM_BASE. */ 25 #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) 26 #define RPI3_PM_RSTS_OFFSET ULL(0x00000020) 27 #define RPI3_PM_WDOG_OFFSET ULL(0x00000024) 28 /* Watchdog constants */ 29 #define RPI3_PM_PASSWORD U(0x5A000000) 30 #define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) 31 #define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) 32 /* 33 * The RSTS register is used by the VideoCore firmware when booting the 34 * Raspberry Pi to know which partition to boot from. The partition value is 35 * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware 36 * to indicate halt. 37 */ 38 #define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) 39 40 /* Make composite power state parameter till power level 0 */ 41 #if PSCI_EXTENDED_STATE_ID 42 43 #define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 44 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 45 ((type) << PSTATE_TYPE_SHIFT)) 46 47 #else 48 49 #define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 50 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 51 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 52 ((type) << PSTATE_TYPE_SHIFT)) 53 54 #endif /* PSCI_EXTENDED_STATE_ID */ 55 56 #define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 57 (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ 58 rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 59 60 /* 61 * The table storing the valid idle power states. Ensure that the 62 * array entries are populated in ascending order of state-id to 63 * enable us to use binary search during power state validation. 64 * The table must be terminated by a NULL entry. 65 */ 66 static const unsigned int rpi3_pm_idle_states[] = { 67 /* State-id - 0x01 */ 68 rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, 69 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), 70 /* State-id - 0x02 */ 71 rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, 72 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), 73 /* State-id - 0x22 */ 74 rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, 75 MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), 76 0, 77 }; 78 79 /******************************************************************************* 80 * Platform handler called to check the validity of the power state 81 * parameter. The power state parameter has to be a composite power state. 82 ******************************************************************************/ 83 static int rpi3_validate_power_state(unsigned int power_state, 84 psci_power_state_t *req_state) 85 { 86 unsigned int state_id; 87 int i; 88 89 assert(req_state != 0); 90 91 /* 92 * Currently we are using a linear search for finding the matching 93 * entry in the idle power state array. This can be made a binary 94 * search if the number of entries justify the additional complexity. 95 */ 96 for (i = 0; rpi3_pm_idle_states[i] != 0; i++) { 97 if (power_state == rpi3_pm_idle_states[i]) { 98 break; 99 } 100 } 101 102 /* Return error if entry not found in the idle state array */ 103 if (!rpi3_pm_idle_states[i]) { 104 return PSCI_E_INVALID_PARAMS; 105 } 106 107 i = 0; 108 state_id = psci_get_pstate_id(power_state); 109 110 /* Parse the State ID and populate the state info parameter */ 111 while (state_id) { 112 req_state->pwr_domain_state[i++] = state_id & 113 PLAT_LOCAL_PSTATE_MASK; 114 state_id >>= PLAT_LOCAL_PSTATE_WIDTH; 115 } 116 117 return PSCI_E_SUCCESS; 118 } 119 120 /******************************************************************************* 121 * Platform handler called when a CPU is about to enter standby. 122 ******************************************************************************/ 123 static void rpi3_cpu_standby(plat_local_state_t cpu_state) 124 { 125 assert(cpu_state == PLAT_LOCAL_STATE_RET); 126 127 /* 128 * Enter standby state. 129 * dsb is good practice before using wfi to enter low power states 130 */ 131 dsb(); 132 wfi(); 133 } 134 135 static void rpi3_pwr_domain_off(const psci_power_state_t *target_state) 136 { 137 #ifdef RPI_HAVE_GIC 138 gicv2_cpuif_disable(); 139 #endif 140 } 141 142 /******************************************************************************* 143 * Platform handler called when a power domain is about to be turned on. The 144 * mpidr determines the CPU to be turned on. 145 ******************************************************************************/ 146 static int rpi3_pwr_domain_on(u_register_t mpidr) 147 { 148 int rc = PSCI_E_SUCCESS; 149 unsigned int pos = plat_core_pos_by_mpidr(mpidr); 150 uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE; 151 152 assert(pos < PLATFORM_CORE_COUNT); 153 154 hold_base += pos * PLAT_RPI3_TM_HOLD_ENTRY_SIZE; 155 156 mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_GO); 157 /* No cache maintenance here, hold_base is mapped as device memory. */ 158 159 /* Make sure that the write has completed */ 160 dsb(); 161 isb(); 162 163 sev(); 164 165 return rc; 166 } 167 168 /******************************************************************************* 169 * Platform handler called when a power domain has just been powered on after 170 * being turned off earlier. The target_state encodes the low power state that 171 * each level has woken up from. 172 ******************************************************************************/ 173 static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) 174 { 175 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == 176 PLAT_LOCAL_STATE_OFF); 177 178 #ifdef RPI_HAVE_GIC 179 gicv2_pcpu_distif_init(); 180 gicv2_cpuif_enable(); 181 #endif 182 } 183 184 static void __dead2 rpi3_pwr_down_wfi( 185 const psci_power_state_t *target_state) 186 { 187 uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE; 188 unsigned int pos = plat_my_core_pos(); 189 190 if (pos == 0) { 191 /* 192 * The secondaries will always be in a wait 193 * for warm boot on reset, but the BSP needs 194 * to be able to distinguish between waiting 195 * for warm boot (e.g. after psci_off, waiting 196 * for psci_on) and a cold boot. 197 */ 198 mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF); 199 /* No cache maintenance here, we run with caches off already. */ 200 dsb(); 201 isb(); 202 } 203 204 write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT); 205 206 while (1) { 207 wfi(); 208 } 209 } 210 211 /******************************************************************************* 212 * Platform handlers for system reset and system off. 213 ******************************************************************************/ 214 215 /* 10 ticks (Watchdog timer = Timer clock / 16) */ 216 #define RESET_TIMEOUT U(10) 217 218 static void __dead2 rpi3_watchdog_reset(void) 219 { 220 uint32_t rstc; 221 222 console_flush(); 223 224 dsbsy(); 225 isb(); 226 227 mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET, 228 RPI3_PM_PASSWORD | RESET_TIMEOUT); 229 230 rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET); 231 rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; 232 rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET; 233 mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc); 234 235 for (;;) { 236 wfi(); 237 } 238 } 239 240 static void __dead2 rpi3_system_reset(void) 241 { 242 INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n"); 243 244 rpi3_watchdog_reset(); 245 } 246 247 static void __dead2 rpi3_system_off(void) 248 { 249 uint32_t rsts; 250 251 INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n"); 252 253 /* 254 * This function doesn't actually make the Raspberry Pi turn itself off, 255 * the hardware doesn't allow it. It simply reboots it and the RSTS 256 * value tells the bootcode.bin firmware not to continue the regular 257 * bootflow and to stay in a low power mode. 258 */ 259 260 rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET); 261 rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT; 262 mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts); 263 264 rpi3_watchdog_reset(); 265 } 266 267 /******************************************************************************* 268 * Platform handlers and setup function. 269 ******************************************************************************/ 270 static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { 271 .cpu_standby = rpi3_cpu_standby, 272 .pwr_domain_off = rpi3_pwr_domain_off, 273 .pwr_domain_on = rpi3_pwr_domain_on, 274 .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, 275 .pwr_domain_pwr_down = rpi3_pwr_down_wfi, 276 .system_off = rpi3_system_off, 277 .system_reset = rpi3_system_reset, 278 .validate_power_state = rpi3_validate_power_state, 279 }; 280 281 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 282 const plat_psci_ops_t **psci_ops) 283 { 284 uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT; 285 286 *entrypoint = sec_entrypoint; 287 *psci_ops = &plat_rpi3_psci_pm_ops; 288 289 return 0; 290 } 291