1*e3ec6ff4SXiaoDong Huang /* 2*e3ec6ff4SXiaoDong Huang * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3*e3ec6ff4SXiaoDong Huang * 4*e3ec6ff4SXiaoDong Huang * SPDX-License-Identifier: BSD-3-Clause 5*e3ec6ff4SXiaoDong Huang */ 6*e3ec6ff4SXiaoDong Huang 7*e3ec6ff4SXiaoDong Huang #ifndef __PLAT_DEF_H__ 8*e3ec6ff4SXiaoDong Huang #define __PLAT_DEF_H__ 9*e3ec6ff4SXiaoDong Huang 10*e3ec6ff4SXiaoDong Huang #define SIZE_K(n) ((n) * 1024) 11*e3ec6ff4SXiaoDong Huang 12*e3ec6ff4SXiaoDong Huang #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) 13*e3ec6ff4SXiaoDong Huang 14*e3ec6ff4SXiaoDong Huang /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15*e3ec6ff4SXiaoDong Huang #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16*e3ec6ff4SXiaoDong Huang 17*e3ec6ff4SXiaoDong Huang #define UMCTL0_BASE 0xf7000000 18*e3ec6ff4SXiaoDong Huang #define UMCTL1_BASE 0xf8000000 19*e3ec6ff4SXiaoDong Huang #define UMCTL2_BASE 0xf9000000 20*e3ec6ff4SXiaoDong Huang #define UMCTL3_BASE 0xfa000000 21*e3ec6ff4SXiaoDong Huang 22*e3ec6ff4SXiaoDong Huang #define GIC600_BASE 0xfe600000 23*e3ec6ff4SXiaoDong Huang #define GIC600_SIZE SIZE_K(64) 24*e3ec6ff4SXiaoDong Huang 25*e3ec6ff4SXiaoDong Huang #define DAPLITE_BASE 0xfd100000 26*e3ec6ff4SXiaoDong Huang #define PMU0SGRF_BASE 0xfd580000 27*e3ec6ff4SXiaoDong Huang #define PMU1SGRF_BASE 0xfd582000 28*e3ec6ff4SXiaoDong Huang #define BUSSGRF_BASE 0xfd586000 29*e3ec6ff4SXiaoDong Huang #define DSUSGRF_BASE 0xfd587000 30*e3ec6ff4SXiaoDong Huang #define PMU0GRF_BASE 0xfd588000 31*e3ec6ff4SXiaoDong Huang #define PMU1GRF_BASE 0xfd58a000 32*e3ec6ff4SXiaoDong Huang 33*e3ec6ff4SXiaoDong Huang #define SYSGRF_BASE 0xfd58c000 34*e3ec6ff4SXiaoDong Huang #define BIGCORE0GRF_BASE 0xfd590000 35*e3ec6ff4SXiaoDong Huang #define BIGCORE1GRF_BASE 0xfd592000 36*e3ec6ff4SXiaoDong Huang #define LITCOREGRF_BASE 0xfd594000 37*e3ec6ff4SXiaoDong Huang #define DSUGRF_BASE 0xfd598000 38*e3ec6ff4SXiaoDong Huang #define DDR01GRF_BASE 0xfd59c000 39*e3ec6ff4SXiaoDong Huang #define DDR23GRF_BASE 0xfd59d000 40*e3ec6ff4SXiaoDong Huang #define CENTERGRF_BASE 0xfd59e000 41*e3ec6ff4SXiaoDong Huang #define GPUGRF_BASE 0xfd5a0000 42*e3ec6ff4SXiaoDong Huang #define NPUGRF_BASE 0xfd5a2000 43*e3ec6ff4SXiaoDong Huang #define USBGRF_BASE 0xfd5ac000 44*e3ec6ff4SXiaoDong Huang #define PHPGRF_BASE 0xfd5b0000 45*e3ec6ff4SXiaoDong Huang #define PCIE3PHYGRF_BASE 0xfd5b8000 46*e3ec6ff4SXiaoDong Huang #define USB2PHY0_GRF_BASE 0xfd5d0000 47*e3ec6ff4SXiaoDong Huang #define USB2PHY1_GRF_BASE 0xfd5d4000 48*e3ec6ff4SXiaoDong Huang #define USB2PHY2_GRF_BASE 0xfd5d8000 49*e3ec6ff4SXiaoDong Huang #define USB2PHY3_GRF_BASE 0xfd5dc000 50*e3ec6ff4SXiaoDong Huang 51*e3ec6ff4SXiaoDong Huang #define PMU0IOC_BASE 0xfd5f0000 52*e3ec6ff4SXiaoDong Huang #define PMU1IOC_BASE 0xfd5f4000 53*e3ec6ff4SXiaoDong Huang #define BUSIOC_BASE 0xfd5f8000 54*e3ec6ff4SXiaoDong Huang #define VCCIO1_4_IOC_BASE 0xfd5f9000 55*e3ec6ff4SXiaoDong Huang #define VCCIO3_5_IOC_BASE 0xfd5fa000 56*e3ec6ff4SXiaoDong Huang #define VCCIO2_IOC_BASE 0xfd5fb000 57*e3ec6ff4SXiaoDong Huang #define VCCIO6_IOC_BASE 0xfd5fc000 58*e3ec6ff4SXiaoDong Huang 59*e3ec6ff4SXiaoDong Huang #define SRAM_BASE 0xff000000 60*e3ec6ff4SXiaoDong Huang #define PMUSRAM_BASE 0xff100000 61*e3ec6ff4SXiaoDong Huang #define PMUSRAM_SIZE SIZE_K(128) 62*e3ec6ff4SXiaoDong Huang #define PMUSRAM_RSIZE SIZE_K(64) 63*e3ec6ff4SXiaoDong Huang 64*e3ec6ff4SXiaoDong Huang #define CRU_BASE 0xfd7c0000 65*e3ec6ff4SXiaoDong Huang #define PHP_CRU_BASE 0xfd7c8000 66*e3ec6ff4SXiaoDong Huang #define SCRU_BASE 0xfd7d0000 67*e3ec6ff4SXiaoDong Huang #define BUSSCRU_BASE 0xfd7d8000 68*e3ec6ff4SXiaoDong Huang #define PMU1SCRU_BASE 0xfd7e0000 69*e3ec6ff4SXiaoDong Huang #define PMU1CRU_BASE 0xfd7f0000 70*e3ec6ff4SXiaoDong Huang 71*e3ec6ff4SXiaoDong Huang #define DDR0CRU_BASE 0xfd800000 72*e3ec6ff4SXiaoDong Huang #define DDR1CRU_BASE 0xfd804000 73*e3ec6ff4SXiaoDong Huang #define DDR2CRU_BASE 0xfd808000 74*e3ec6ff4SXiaoDong Huang #define DDR3CRU_BASE 0xfd80c000 75*e3ec6ff4SXiaoDong Huang 76*e3ec6ff4SXiaoDong Huang #define BIGCORE0CRU_BASE 0xfd810000 77*e3ec6ff4SXiaoDong Huang #define BIGCORE1CRU_BASE 0xfd812000 78*e3ec6ff4SXiaoDong Huang #define LITCRU_BASE 0xfd814000 79*e3ec6ff4SXiaoDong Huang #define DSUCRU_BASE 0xfd818000 80*e3ec6ff4SXiaoDong Huang 81*e3ec6ff4SXiaoDong Huang #define I2C0_BASE 0xfd880000 82*e3ec6ff4SXiaoDong Huang #define UART0_BASE 0xfd890000 83*e3ec6ff4SXiaoDong Huang #define GPIO0_BASE 0xfd8a0000 84*e3ec6ff4SXiaoDong Huang #define PWM0_BASE 0xfd8b0000 85*e3ec6ff4SXiaoDong Huang #define PMUPVTM_BASE 0xfd8c0000 86*e3ec6ff4SXiaoDong Huang #define TIMER_HP_BASE 0xfd8c8000 87*e3ec6ff4SXiaoDong Huang #define PMU0_BASE 0xfd8d0000 88*e3ec6ff4SXiaoDong Huang #define PMU1_BASE 0xfd8d4000 89*e3ec6ff4SXiaoDong Huang #define PMU2_BASE 0xfd8d8000 90*e3ec6ff4SXiaoDong Huang #define PMU_BASE PMU0_BASE 91*e3ec6ff4SXiaoDong Huang #define PMUWDT_BASE 0xfd8e0000 92*e3ec6ff4SXiaoDong Huang #define PMUTIMER_BASE 0xfd8f0000 93*e3ec6ff4SXiaoDong Huang #define OSC_CHK_BASE 0xfd9b0000 94*e3ec6ff4SXiaoDong Huang #define VOP_BASE 0xfdd90000 95*e3ec6ff4SXiaoDong Huang #define HDMIRX_BASE 0xfdee0000 96*e3ec6ff4SXiaoDong Huang 97*e3ec6ff4SXiaoDong Huang #define MSCH0_BASE 0xfe000000 98*e3ec6ff4SXiaoDong Huang #define MSCH1_BASE 0xfe002000 99*e3ec6ff4SXiaoDong Huang #define MSCH2_BASE 0xfe004000 100*e3ec6ff4SXiaoDong Huang #define MSCH3_BASE 0xfe006000 101*e3ec6ff4SXiaoDong Huang #define FIREWALL_DSU_BASE 0xfe010000 102*e3ec6ff4SXiaoDong Huang #define FIREWALL_DDR_BASE 0xfe030000 103*e3ec6ff4SXiaoDong Huang #define FIREWALL_SYSMEM_BASE 0xfe038000 104*e3ec6ff4SXiaoDong Huang #define DDRPHY0_BASE 0xfe0c0000 105*e3ec6ff4SXiaoDong Huang #define DDRPHY1_BASE 0xfe0d0000 106*e3ec6ff4SXiaoDong Huang #define DDRPHY2_BASE 0xfe0e0000 107*e3ec6ff4SXiaoDong Huang #define DDRPHY3_BASE 0xfe0f0000 108*e3ec6ff4SXiaoDong Huang #define TIMER_DDR_BASE 0xfe118000 109*e3ec6ff4SXiaoDong Huang #define KEYLADDER_BASE 0xfe380000 110*e3ec6ff4SXiaoDong Huang #define CRYPTO_S_BASE 0xfe390000 111*e3ec6ff4SXiaoDong Huang #define OTP_S_BASE 0xfe3a0000 112*e3ec6ff4SXiaoDong Huang #define DCF_BASE 0xfe3c0000 113*e3ec6ff4SXiaoDong Huang #define STIMER0_BASE 0xfe3d0000 114*e3ec6ff4SXiaoDong Huang #define WDT_S_BASE 0xfe3e0000 115*e3ec6ff4SXiaoDong Huang #define CRYPTO_S_BY_KEYLAD_BASE 0xfe420000 116*e3ec6ff4SXiaoDong Huang #define NSTIMER0_BASE 0xfeae0000 117*e3ec6ff4SXiaoDong Huang #define NSTIMER1_BASE 0xfeae8000 118*e3ec6ff4SXiaoDong Huang #define WDT_NS_BASE 0xfeaf0000 119*e3ec6ff4SXiaoDong Huang 120*e3ec6ff4SXiaoDong Huang #define UART1_BASE 0xfeb40000 121*e3ec6ff4SXiaoDong Huang #define UART2_BASE 0xfeb50000 122*e3ec6ff4SXiaoDong Huang #define UART3_BASE 0xfeb60000 123*e3ec6ff4SXiaoDong Huang #define UART4_BASE 0xfeb70000 124*e3ec6ff4SXiaoDong Huang #define UART5_BASE 0xfeb80000 125*e3ec6ff4SXiaoDong Huang #define UART6_BASE 0xfeb90000 126*e3ec6ff4SXiaoDong Huang #define UART7_BASE 0xfeba0000 127*e3ec6ff4SXiaoDong Huang #define UART8_BASE 0xfebb0000 128*e3ec6ff4SXiaoDong Huang #define UART9_BASE 0xfebc0000 129*e3ec6ff4SXiaoDong Huang 130*e3ec6ff4SXiaoDong Huang #define GPIO1_BASE 0xfec20000 131*e3ec6ff4SXiaoDong Huang #define GPIO2_BASE 0xfec30000 132*e3ec6ff4SXiaoDong Huang #define GPIO3_BASE 0xfec40000 133*e3ec6ff4SXiaoDong Huang #define GPIO4_BASE 0xfec50000 134*e3ec6ff4SXiaoDong Huang 135*e3ec6ff4SXiaoDong Huang #define MAILBOX1_BASE 0xfec70000 136*e3ec6ff4SXiaoDong Huang #define OTP_NS_BASE 0xfecc0000 137*e3ec6ff4SXiaoDong Huang #define INTMUX0_DDR_BASE 0Xfecf8000 138*e3ec6ff4SXiaoDong Huang #define INTMUX1_DDR_BASE 0Xfecfc000 139*e3ec6ff4SXiaoDong Huang #define STIMER1_BASE 0xfed30000 140*e3ec6ff4SXiaoDong Huang 141*e3ec6ff4SXiaoDong Huang /************************************************************************** 142*e3ec6ff4SXiaoDong Huang * sys sram allocation 143*e3ec6ff4SXiaoDong Huang **************************************************************************/ 144*e3ec6ff4SXiaoDong Huang #define SRAM_ENTRY_BASE SRAM_BASE 145*e3ec6ff4SXiaoDong Huang #define SRAM_PMUM0_SHMEM_BASE (SRAM_ENTRY_BASE + SIZE_K(3)) 146*e3ec6ff4SXiaoDong Huang #define SRAM_LD_BASE (SRAM_ENTRY_BASE + SIZE_K(4)) 147*e3ec6ff4SXiaoDong Huang #define SRAM_LD_SIZE SIZE_K(64) 148*e3ec6ff4SXiaoDong Huang 149*e3ec6ff4SXiaoDong Huang #define SRAM_LD_SP (SRAM_LD_BASE + SRAM_LD_SIZE -\ 150*e3ec6ff4SXiaoDong Huang 128) 151*e3ec6ff4SXiaoDong Huang 152*e3ec6ff4SXiaoDong Huang /************************************************************************** 153*e3ec6ff4SXiaoDong Huang * share mem region allocation: 1M~2M 154*e3ec6ff4SXiaoDong Huang **************************************************************************/ 155*e3ec6ff4SXiaoDong Huang #define DDR_SHARE_MEM SIZE_K(1024) 156*e3ec6ff4SXiaoDong Huang #define DDR_SHARE_SIZE SIZE_K(64) 157*e3ec6ff4SXiaoDong Huang 158*e3ec6ff4SXiaoDong Huang #define SHARE_MEM_BASE DDR_SHARE_MEM 159*e3ec6ff4SXiaoDong Huang #define SHARE_MEM_PAGE_NUM 15 160*e3ec6ff4SXiaoDong Huang #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 161*e3ec6ff4SXiaoDong Huang 162*e3ec6ff4SXiaoDong Huang #define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE) 163*e3ec6ff4SXiaoDong Huang #define SCMI_SHARE_MEM_SIZE SIZE_K(4) 164*e3ec6ff4SXiaoDong Huang 165*e3ec6ff4SXiaoDong Huang /************************************************************************** 166*e3ec6ff4SXiaoDong Huang * UART related constants 167*e3ec6ff4SXiaoDong Huang **************************************************************************/ 168*e3ec6ff4SXiaoDong Huang #define RK_DBG_UART_BASE UART2_BASE 169*e3ec6ff4SXiaoDong Huang #define RK_DBG_UART_BAUDRATE 1500000 170*e3ec6ff4SXiaoDong Huang #define RK_DBG_UART_CLOCK 24000000 171*e3ec6ff4SXiaoDong Huang 172*e3ec6ff4SXiaoDong Huang /****************************************************************************** 173*e3ec6ff4SXiaoDong Huang * System counter frequency related constants 174*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 175*e3ec6ff4SXiaoDong Huang #define SYS_COUNTER_FREQ_IN_TICKS 24000000 176*e3ec6ff4SXiaoDong Huang #define SYS_COUNTER_FREQ_IN_MHZ 24 177*e3ec6ff4SXiaoDong Huang 178*e3ec6ff4SXiaoDong Huang /****************************************************************************** 179*e3ec6ff4SXiaoDong Huang * GIC-600 & interrupt handling related constants 180*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 181*e3ec6ff4SXiaoDong Huang 182*e3ec6ff4SXiaoDong Huang /* Base rk_platform compatible GIC memory map */ 183*e3ec6ff4SXiaoDong Huang #define PLAT_GICD_BASE GIC600_BASE 184*e3ec6ff4SXiaoDong Huang #define PLAT_GICC_BASE 0 185*e3ec6ff4SXiaoDong Huang #define PLAT_GICR_BASE (GIC600_BASE + 0x80000) 186*e3ec6ff4SXiaoDong Huang #define PLAT_GICITS0_BASE 0xfe640000 187*e3ec6ff4SXiaoDong Huang #define PLAT_GICITS1_BASE 0xfe660000 188*e3ec6ff4SXiaoDong Huang 189*e3ec6ff4SXiaoDong Huang /****************************************************************************** 190*e3ec6ff4SXiaoDong Huang * sgi, ppi 191*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 192*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_0 8 193*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_1 9 194*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_2 10 195*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_3 11 196*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_4 12 197*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_5 13 198*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_6 14 199*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_7 15 200*e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_PHY_TIMER 29 201*e3ec6ff4SXiaoDong Huang 202*e3ec6ff4SXiaoDong Huang /* 203*e3ec6ff4SXiaoDong Huang * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 204*e3ec6ff4SXiaoDong Huang * terminology. On a GICv2 system or mode, the lists will be merged and treated 205*e3ec6ff4SXiaoDong Huang * as Group 0 interrupts. 206*e3ec6ff4SXiaoDong Huang */ 207*e3ec6ff4SXiaoDong Huang 208*e3ec6ff4SXiaoDong Huang #define PLAT_RK_GICV3_G1S_IRQS \ 209*e3ec6ff4SXiaoDong Huang INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 210*e3ec6ff4SXiaoDong Huang INTR_GROUP1S, GIC_INTR_CFG_LEVEL) 211*e3ec6ff4SXiaoDong Huang 212*e3ec6ff4SXiaoDong Huang #define PLAT_RK_GICV3_G0_IRQS \ 213*e3ec6ff4SXiaoDong Huang INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 214*e3ec6ff4SXiaoDong Huang INTR_GROUP0, GIC_INTR_CFG_LEVEL) 215*e3ec6ff4SXiaoDong Huang 216*e3ec6ff4SXiaoDong Huang /****************************************************************************** 217*e3ec6ff4SXiaoDong Huang * pm reg region memory 218*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 219*e3ec6ff4SXiaoDong Huang #define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(4) 220*e3ec6ff4SXiaoDong Huang 221*e3ec6ff4SXiaoDong Huang #endif /* __PLAT_DEF_H__ */ 222