1e3ec6ff4SXiaoDong Huang /* 2e3ec6ff4SXiaoDong Huang * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3e3ec6ff4SXiaoDong Huang * 4e3ec6ff4SXiaoDong Huang * SPDX-License-Identifier: BSD-3-Clause 5e3ec6ff4SXiaoDong Huang */ 6e3ec6ff4SXiaoDong Huang 7e3ec6ff4SXiaoDong Huang #ifndef __PLAT_DEF_H__ 8e3ec6ff4SXiaoDong Huang #define __PLAT_DEF_H__ 9e3ec6ff4SXiaoDong Huang 10e3ec6ff4SXiaoDong Huang #define SIZE_K(n) ((n) * 1024) 11e3ec6ff4SXiaoDong Huang 12e3ec6ff4SXiaoDong Huang #define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits)) 13e3ec6ff4SXiaoDong Huang 14e3ec6ff4SXiaoDong Huang /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15e3ec6ff4SXiaoDong Huang #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16e3ec6ff4SXiaoDong Huang 17e3ec6ff4SXiaoDong Huang #define UMCTL0_BASE 0xf7000000 18e3ec6ff4SXiaoDong Huang #define UMCTL1_BASE 0xf8000000 19e3ec6ff4SXiaoDong Huang #define UMCTL2_BASE 0xf9000000 20e3ec6ff4SXiaoDong Huang #define UMCTL3_BASE 0xfa000000 21e3ec6ff4SXiaoDong Huang 22e3ec6ff4SXiaoDong Huang #define GIC600_BASE 0xfe600000 23e3ec6ff4SXiaoDong Huang #define GIC600_SIZE SIZE_K(64) 24e3ec6ff4SXiaoDong Huang 25e3ec6ff4SXiaoDong Huang #define DAPLITE_BASE 0xfd100000 26e3ec6ff4SXiaoDong Huang #define PMU0SGRF_BASE 0xfd580000 27e3ec6ff4SXiaoDong Huang #define PMU1SGRF_BASE 0xfd582000 28e3ec6ff4SXiaoDong Huang #define BUSSGRF_BASE 0xfd586000 29e3ec6ff4SXiaoDong Huang #define DSUSGRF_BASE 0xfd587000 30e3ec6ff4SXiaoDong Huang #define PMU0GRF_BASE 0xfd588000 31e3ec6ff4SXiaoDong Huang #define PMU1GRF_BASE 0xfd58a000 32e3ec6ff4SXiaoDong Huang 33e3ec6ff4SXiaoDong Huang #define SYSGRF_BASE 0xfd58c000 34e3ec6ff4SXiaoDong Huang #define BIGCORE0GRF_BASE 0xfd590000 35e3ec6ff4SXiaoDong Huang #define BIGCORE1GRF_BASE 0xfd592000 36e3ec6ff4SXiaoDong Huang #define LITCOREGRF_BASE 0xfd594000 37e3ec6ff4SXiaoDong Huang #define DSUGRF_BASE 0xfd598000 38e3ec6ff4SXiaoDong Huang #define DDR01GRF_BASE 0xfd59c000 39e3ec6ff4SXiaoDong Huang #define DDR23GRF_BASE 0xfd59d000 40e3ec6ff4SXiaoDong Huang #define CENTERGRF_BASE 0xfd59e000 41e3ec6ff4SXiaoDong Huang #define GPUGRF_BASE 0xfd5a0000 42e3ec6ff4SXiaoDong Huang #define NPUGRF_BASE 0xfd5a2000 43e3ec6ff4SXiaoDong Huang #define USBGRF_BASE 0xfd5ac000 44e3ec6ff4SXiaoDong Huang #define PHPGRF_BASE 0xfd5b0000 45e3ec6ff4SXiaoDong Huang #define PCIE3PHYGRF_BASE 0xfd5b8000 46e3ec6ff4SXiaoDong Huang #define USB2PHY0_GRF_BASE 0xfd5d0000 47e3ec6ff4SXiaoDong Huang #define USB2PHY1_GRF_BASE 0xfd5d4000 48e3ec6ff4SXiaoDong Huang #define USB2PHY2_GRF_BASE 0xfd5d8000 49e3ec6ff4SXiaoDong Huang #define USB2PHY3_GRF_BASE 0xfd5dc000 50e3ec6ff4SXiaoDong Huang 51e3ec6ff4SXiaoDong Huang #define PMU0IOC_BASE 0xfd5f0000 52e3ec6ff4SXiaoDong Huang #define PMU1IOC_BASE 0xfd5f4000 53e3ec6ff4SXiaoDong Huang #define BUSIOC_BASE 0xfd5f8000 54e3ec6ff4SXiaoDong Huang #define VCCIO1_4_IOC_BASE 0xfd5f9000 55e3ec6ff4SXiaoDong Huang #define VCCIO3_5_IOC_BASE 0xfd5fa000 56e3ec6ff4SXiaoDong Huang #define VCCIO2_IOC_BASE 0xfd5fb000 57e3ec6ff4SXiaoDong Huang #define VCCIO6_IOC_BASE 0xfd5fc000 58e3ec6ff4SXiaoDong Huang 59e3ec6ff4SXiaoDong Huang #define SRAM_BASE 0xff000000 60e3ec6ff4SXiaoDong Huang #define PMUSRAM_BASE 0xff100000 61e3ec6ff4SXiaoDong Huang #define PMUSRAM_SIZE SIZE_K(128) 62e3ec6ff4SXiaoDong Huang #define PMUSRAM_RSIZE SIZE_K(64) 63e3ec6ff4SXiaoDong Huang 64e3ec6ff4SXiaoDong Huang #define CRU_BASE 0xfd7c0000 65e3ec6ff4SXiaoDong Huang #define PHP_CRU_BASE 0xfd7c8000 66e3ec6ff4SXiaoDong Huang #define SCRU_BASE 0xfd7d0000 67e3ec6ff4SXiaoDong Huang #define BUSSCRU_BASE 0xfd7d8000 68e3ec6ff4SXiaoDong Huang #define PMU1SCRU_BASE 0xfd7e0000 69e3ec6ff4SXiaoDong Huang #define PMU1CRU_BASE 0xfd7f0000 70e3ec6ff4SXiaoDong Huang 71e3ec6ff4SXiaoDong Huang #define DDR0CRU_BASE 0xfd800000 72e3ec6ff4SXiaoDong Huang #define DDR1CRU_BASE 0xfd804000 73e3ec6ff4SXiaoDong Huang #define DDR2CRU_BASE 0xfd808000 74e3ec6ff4SXiaoDong Huang #define DDR3CRU_BASE 0xfd80c000 75e3ec6ff4SXiaoDong Huang 76e3ec6ff4SXiaoDong Huang #define BIGCORE0CRU_BASE 0xfd810000 77e3ec6ff4SXiaoDong Huang #define BIGCORE1CRU_BASE 0xfd812000 78e3ec6ff4SXiaoDong Huang #define LITCRU_BASE 0xfd814000 79e3ec6ff4SXiaoDong Huang #define DSUCRU_BASE 0xfd818000 80e3ec6ff4SXiaoDong Huang 81e3ec6ff4SXiaoDong Huang #define I2C0_BASE 0xfd880000 82e3ec6ff4SXiaoDong Huang #define UART0_BASE 0xfd890000 83e3ec6ff4SXiaoDong Huang #define GPIO0_BASE 0xfd8a0000 84e3ec6ff4SXiaoDong Huang #define PWM0_BASE 0xfd8b0000 85e3ec6ff4SXiaoDong Huang #define PMUPVTM_BASE 0xfd8c0000 86e3ec6ff4SXiaoDong Huang #define TIMER_HP_BASE 0xfd8c8000 87e3ec6ff4SXiaoDong Huang #define PMU0_BASE 0xfd8d0000 88e3ec6ff4SXiaoDong Huang #define PMU1_BASE 0xfd8d4000 89e3ec6ff4SXiaoDong Huang #define PMU2_BASE 0xfd8d8000 90e3ec6ff4SXiaoDong Huang #define PMU_BASE PMU0_BASE 91e3ec6ff4SXiaoDong Huang #define PMUWDT_BASE 0xfd8e0000 92e3ec6ff4SXiaoDong Huang #define PMUTIMER_BASE 0xfd8f0000 93e3ec6ff4SXiaoDong Huang #define OSC_CHK_BASE 0xfd9b0000 94e3ec6ff4SXiaoDong Huang #define VOP_BASE 0xfdd90000 95e3ec6ff4SXiaoDong Huang #define HDMIRX_BASE 0xfdee0000 96e3ec6ff4SXiaoDong Huang 97e3ec6ff4SXiaoDong Huang #define MSCH0_BASE 0xfe000000 98e3ec6ff4SXiaoDong Huang #define MSCH1_BASE 0xfe002000 99e3ec6ff4SXiaoDong Huang #define MSCH2_BASE 0xfe004000 100e3ec6ff4SXiaoDong Huang #define MSCH3_BASE 0xfe006000 101e3ec6ff4SXiaoDong Huang #define FIREWALL_DSU_BASE 0xfe010000 102e3ec6ff4SXiaoDong Huang #define FIREWALL_DDR_BASE 0xfe030000 103e3ec6ff4SXiaoDong Huang #define FIREWALL_SYSMEM_BASE 0xfe038000 104e3ec6ff4SXiaoDong Huang #define DDRPHY0_BASE 0xfe0c0000 105e3ec6ff4SXiaoDong Huang #define DDRPHY1_BASE 0xfe0d0000 106e3ec6ff4SXiaoDong Huang #define DDRPHY2_BASE 0xfe0e0000 107e3ec6ff4SXiaoDong Huang #define DDRPHY3_BASE 0xfe0f0000 108e3ec6ff4SXiaoDong Huang #define TIMER_DDR_BASE 0xfe118000 109e3ec6ff4SXiaoDong Huang #define KEYLADDER_BASE 0xfe380000 110e3ec6ff4SXiaoDong Huang #define CRYPTO_S_BASE 0xfe390000 111e3ec6ff4SXiaoDong Huang #define OTP_S_BASE 0xfe3a0000 112e3ec6ff4SXiaoDong Huang #define DCF_BASE 0xfe3c0000 113e3ec6ff4SXiaoDong Huang #define STIMER0_BASE 0xfe3d0000 114e3ec6ff4SXiaoDong Huang #define WDT_S_BASE 0xfe3e0000 115e3ec6ff4SXiaoDong Huang #define CRYPTO_S_BY_KEYLAD_BASE 0xfe420000 116e3ec6ff4SXiaoDong Huang #define NSTIMER0_BASE 0xfeae0000 117e3ec6ff4SXiaoDong Huang #define NSTIMER1_BASE 0xfeae8000 118e3ec6ff4SXiaoDong Huang #define WDT_NS_BASE 0xfeaf0000 119e3ec6ff4SXiaoDong Huang 120e3ec6ff4SXiaoDong Huang #define UART1_BASE 0xfeb40000 121e3ec6ff4SXiaoDong Huang #define UART2_BASE 0xfeb50000 122e3ec6ff4SXiaoDong Huang #define UART3_BASE 0xfeb60000 123e3ec6ff4SXiaoDong Huang #define UART4_BASE 0xfeb70000 124e3ec6ff4SXiaoDong Huang #define UART5_BASE 0xfeb80000 125e3ec6ff4SXiaoDong Huang #define UART6_BASE 0xfeb90000 126e3ec6ff4SXiaoDong Huang #define UART7_BASE 0xfeba0000 127e3ec6ff4SXiaoDong Huang #define UART8_BASE 0xfebb0000 128e3ec6ff4SXiaoDong Huang #define UART9_BASE 0xfebc0000 129e3ec6ff4SXiaoDong Huang 130e3ec6ff4SXiaoDong Huang #define GPIO1_BASE 0xfec20000 131e3ec6ff4SXiaoDong Huang #define GPIO2_BASE 0xfec30000 132e3ec6ff4SXiaoDong Huang #define GPIO3_BASE 0xfec40000 133e3ec6ff4SXiaoDong Huang #define GPIO4_BASE 0xfec50000 134e3ec6ff4SXiaoDong Huang 135e3ec6ff4SXiaoDong Huang #define MAILBOX1_BASE 0xfec70000 136e3ec6ff4SXiaoDong Huang #define OTP_NS_BASE 0xfecc0000 137e3ec6ff4SXiaoDong Huang #define INTMUX0_DDR_BASE 0Xfecf8000 138e3ec6ff4SXiaoDong Huang #define INTMUX1_DDR_BASE 0Xfecfc000 139e3ec6ff4SXiaoDong Huang #define STIMER1_BASE 0xfed30000 140e3ec6ff4SXiaoDong Huang 141e3ec6ff4SXiaoDong Huang /************************************************************************** 142e3ec6ff4SXiaoDong Huang * sys sram allocation 143e3ec6ff4SXiaoDong Huang **************************************************************************/ 144e3ec6ff4SXiaoDong Huang #define SRAM_ENTRY_BASE SRAM_BASE 145e3ec6ff4SXiaoDong Huang #define SRAM_PMUM0_SHMEM_BASE (SRAM_ENTRY_BASE + SIZE_K(3)) 146e3ec6ff4SXiaoDong Huang #define SRAM_LD_BASE (SRAM_ENTRY_BASE + SIZE_K(4)) 147e3ec6ff4SXiaoDong Huang #define SRAM_LD_SIZE SIZE_K(64) 148e3ec6ff4SXiaoDong Huang 149e3ec6ff4SXiaoDong Huang #define SRAM_LD_SP (SRAM_LD_BASE + SRAM_LD_SIZE -\ 150e3ec6ff4SXiaoDong Huang 128) 151e3ec6ff4SXiaoDong Huang 152e3ec6ff4SXiaoDong Huang /************************************************************************** 153e3ec6ff4SXiaoDong Huang * share mem region allocation: 1M~2M 154e3ec6ff4SXiaoDong Huang **************************************************************************/ 155e3ec6ff4SXiaoDong Huang #define DDR_SHARE_MEM SIZE_K(1024) 156e3ec6ff4SXiaoDong Huang #define DDR_SHARE_SIZE SIZE_K(64) 157e3ec6ff4SXiaoDong Huang 158e3ec6ff4SXiaoDong Huang #define SHARE_MEM_BASE DDR_SHARE_MEM 159e3ec6ff4SXiaoDong Huang #define SHARE_MEM_PAGE_NUM 15 160e3ec6ff4SXiaoDong Huang #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 161e3ec6ff4SXiaoDong Huang 162e3ec6ff4SXiaoDong Huang #define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE) 163e3ec6ff4SXiaoDong Huang #define SCMI_SHARE_MEM_SIZE SIZE_K(4) 164e3ec6ff4SXiaoDong Huang 165*04150feeSXiaoDong Huang #define SMT_BUFFER_BASE SCMI_SHARE_MEM_BASE 166*04150feeSXiaoDong Huang #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 167*04150feeSXiaoDong Huang 168e3ec6ff4SXiaoDong Huang /************************************************************************** 169e3ec6ff4SXiaoDong Huang * UART related constants 170e3ec6ff4SXiaoDong Huang **************************************************************************/ 171e3ec6ff4SXiaoDong Huang #define RK_DBG_UART_BASE UART2_BASE 172e3ec6ff4SXiaoDong Huang #define RK_DBG_UART_BAUDRATE 1500000 173e3ec6ff4SXiaoDong Huang #define RK_DBG_UART_CLOCK 24000000 174e3ec6ff4SXiaoDong Huang 175e3ec6ff4SXiaoDong Huang /****************************************************************************** 176e3ec6ff4SXiaoDong Huang * System counter frequency related constants 177e3ec6ff4SXiaoDong Huang ******************************************************************************/ 178e3ec6ff4SXiaoDong Huang #define SYS_COUNTER_FREQ_IN_TICKS 24000000 179e3ec6ff4SXiaoDong Huang #define SYS_COUNTER_FREQ_IN_MHZ 24 180e3ec6ff4SXiaoDong Huang 181e3ec6ff4SXiaoDong Huang /****************************************************************************** 182e3ec6ff4SXiaoDong Huang * GIC-600 & interrupt handling related constants 183e3ec6ff4SXiaoDong Huang ******************************************************************************/ 184e3ec6ff4SXiaoDong Huang 185e3ec6ff4SXiaoDong Huang /* Base rk_platform compatible GIC memory map */ 186e3ec6ff4SXiaoDong Huang #define PLAT_GICD_BASE GIC600_BASE 187e3ec6ff4SXiaoDong Huang #define PLAT_GICC_BASE 0 188e3ec6ff4SXiaoDong Huang #define PLAT_GICR_BASE (GIC600_BASE + 0x80000) 189e3ec6ff4SXiaoDong Huang #define PLAT_GICITS0_BASE 0xfe640000 190e3ec6ff4SXiaoDong Huang #define PLAT_GICITS1_BASE 0xfe660000 191e3ec6ff4SXiaoDong Huang 192e3ec6ff4SXiaoDong Huang /****************************************************************************** 193e3ec6ff4SXiaoDong Huang * sgi, ppi 194e3ec6ff4SXiaoDong Huang ******************************************************************************/ 195e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_0 8 196e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_1 9 197e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_2 10 198e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_3 11 199e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_4 12 200e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_5 13 201e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_6 14 202e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_SGI_7 15 203e3ec6ff4SXiaoDong Huang #define RK_IRQ_SEC_PHY_TIMER 29 204e3ec6ff4SXiaoDong Huang 205e3ec6ff4SXiaoDong Huang /* 206e3ec6ff4SXiaoDong Huang * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 207e3ec6ff4SXiaoDong Huang * terminology. On a GICv2 system or mode, the lists will be merged and treated 208e3ec6ff4SXiaoDong Huang * as Group 0 interrupts. 209e3ec6ff4SXiaoDong Huang */ 210e3ec6ff4SXiaoDong Huang 211e3ec6ff4SXiaoDong Huang #define PLAT_RK_GICV3_G1S_IRQS \ 212e3ec6ff4SXiaoDong Huang INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 213e3ec6ff4SXiaoDong Huang INTR_GROUP1S, GIC_INTR_CFG_LEVEL) 214e3ec6ff4SXiaoDong Huang 215e3ec6ff4SXiaoDong Huang #define PLAT_RK_GICV3_G0_IRQS \ 216e3ec6ff4SXiaoDong Huang INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 217e3ec6ff4SXiaoDong Huang INTR_GROUP0, GIC_INTR_CFG_LEVEL) 218e3ec6ff4SXiaoDong Huang 219e3ec6ff4SXiaoDong Huang /****************************************************************************** 220e3ec6ff4SXiaoDong Huang * pm reg region memory 221e3ec6ff4SXiaoDong Huang ******************************************************************************/ 222e3ec6ff4SXiaoDong Huang #define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(4) 223e3ec6ff4SXiaoDong Huang 224e3ec6ff4SXiaoDong Huang #endif /* __PLAT_DEF_H__ */ 225