1# 2# Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7RK_PLAT := plat/rockchip 8RK_PLAT_SOC := ${RK_PLAT}/${PLAT} 9RK_PLAT_COMMON := ${RK_PLAT}/common 10 11DISABLE_BIN_GENERATION := 1 12include lib/libfdt/libfdt.mk 13include lib/xlat_tables_v2/xlat_tables.mk 14 15# GIC-600 configuration 16GICV3_IMPL := GIC600 17GICV3_SUPPORT_GIC600 := 1 18 19# Include GICv3 driver files 20include drivers/arm/gic/v3/gicv3.mk 21 22PLAT_INCLUDES := -Iinclude/plat/common \ 23 -Idrivers/arm/gic/v3/ \ 24 -Idrivers/scmi-msg/ \ 25 -I${RK_PLAT_COMMON}/ \ 26 -I${RK_PLAT_COMMON}/drivers/pmu/ \ 27 -I${RK_PLAT_COMMON}/drivers/parameter/ \ 28 -I${RK_PLAT_COMMON}/include/ \ 29 -I${RK_PLAT_COMMON}/pmusram/ \ 30 -I${RK_PLAT_COMMON}/scmi/ \ 31 -I${RK_PLAT_SOC}/ \ 32 -I${RK_PLAT_SOC}/drivers/pmu/ \ 33 -I${RK_PLAT_SOC}/drivers/scmi/ \ 34 -I${RK_PLAT_SOC}/drivers/secure/ \ 35 -I${RK_PLAT_SOC}/drivers/soc/ \ 36 -I${RK_PLAT_SOC}/include/ 37 38RK_GIC_SOURCES := ${GICV3_SOURCES} \ 39 plat/common/plat_gicv3.c \ 40 ${RK_PLAT}/common/rockchip_gicv3.c 41 42PLAT_BL_COMMON_SOURCES := ${XLAT_TABLES_LIB_SRCS} \ 43 common/desc_image_load.c \ 44 plat/common/aarch64/crash_console_helpers.S \ 45 lib/bl_aux_params/bl_aux_params.c \ 46 plat/common/plat_psci_common.c 47 48ifneq (${ENABLE_STACK_PROTECTOR},0) 49PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c 50endif 51 52BL31_SOURCES += ${RK_GIC_SOURCES} \ 53 drivers/ti/uart/aarch64/16550_console.S \ 54 drivers/delay_timer/delay_timer.c \ 55 drivers/delay_timer/generic_delay_timer.c \ 56 drivers/scmi-msg/base.c \ 57 drivers/scmi-msg/clock.c \ 58 drivers/scmi-msg/entry.c \ 59 drivers/scmi-msg/reset_domain.c \ 60 drivers/scmi-msg/smt.c \ 61 lib/cpus/aarch64/cortex_a55.S \ 62 lib/cpus/aarch64/cortex_a76.S \ 63 ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ 64 ${RK_PLAT_COMMON}/aarch64/platform_common.c \ 65 ${RK_PLAT_COMMON}/bl31_plat_setup.c \ 66 ${RK_PLAT_COMMON}/plat_pm.c \ 67 ${RK_PLAT_COMMON}/plat_pm_helpers.c \ 68 ${RK_PLAT_COMMON}/plat_topology.c \ 69 ${RK_PLAT_COMMON}/params_setup.c \ 70 ${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \ 71 ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ 72 ${RK_PLAT_COMMON}/scmi/scmi.c \ 73 ${RK_PLAT_COMMON}/scmi/scmi_clock.c \ 74 ${RK_PLAT_COMMON}/scmi/scmi_rstd.c \ 75 ${RK_PLAT_SOC}/plat_sip_calls.c \ 76 ${RK_PLAT_SOC}/drivers/secure/secure.c \ 77 ${RK_PLAT_SOC}/drivers/soc/soc.c \ 78 ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ 79 ${RK_PLAT_SOC}/drivers/pmu/pm_pd_regs.c \ 80 ${RK_PLAT_SOC}/drivers/scmi/rk3588_clk.c \ 81 ${RK_PLAT_SOC}/drivers/scmi/rk3588_rstd.c 82 83CTX_INCLUDE_AARCH32_REGS := 0 84ENABLE_PLAT_COMPAT := 0 85MULTI_CONSOLE_API := 1 86ERRATA_A55_1530923 := 1 87 88# System coherency is managed in hardware 89HW_ASSISTED_COHERENCY := 1 90 91# When building for systems with hardware-assisted coherency, there's no need to 92# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 93USE_COHERENT_MEM := 0 94 95ENABLE_SPE_FOR_LOWER_ELS := 0 96 97PLAT_EXTRA_LD_SCRIPT := 1 98$(eval $(call add_define,PLAT_RK_CPU_RESET_EARLY)) 99