1*e3ec6ff4SXiaoDong Huang /* 2*e3ec6ff4SXiaoDong Huang * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3*e3ec6ff4SXiaoDong Huang * 4*e3ec6ff4SXiaoDong Huang * SPDX-License-Identifier: BSD-3-Clause 5*e3ec6ff4SXiaoDong Huang */ 6*e3ec6ff4SXiaoDong Huang 7*e3ec6ff4SXiaoDong Huang #ifndef __PLATFORM_DEF_H__ 8*e3ec6ff4SXiaoDong Huang #define __PLATFORM_DEF_H__ 9*e3ec6ff4SXiaoDong Huang 10*e3ec6ff4SXiaoDong Huang #include <arch.h> 11*e3ec6ff4SXiaoDong Huang #include <plat/common/common_def.h> 12*e3ec6ff4SXiaoDong Huang 13*e3ec6ff4SXiaoDong Huang #include <rk3588_def.h> 14*e3ec6ff4SXiaoDong Huang 15*e3ec6ff4SXiaoDong Huang #define DEBUG_XLAT_TABLE 0 16*e3ec6ff4SXiaoDong Huang 17*e3ec6ff4SXiaoDong Huang /******************************************************************************* 18*e3ec6ff4SXiaoDong Huang * Platform binary types for linking 19*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 20*e3ec6ff4SXiaoDong Huang #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 21*e3ec6ff4SXiaoDong Huang #define PLATFORM_LINKER_ARCH aarch64 22*e3ec6ff4SXiaoDong Huang 23*e3ec6ff4SXiaoDong Huang /******************************************************************************* 24*e3ec6ff4SXiaoDong Huang * Generic platform constants 25*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 26*e3ec6ff4SXiaoDong Huang 27*e3ec6ff4SXiaoDong Huang /* Size of cacheable stacks */ 28*e3ec6ff4SXiaoDong Huang #if DEBUG_XLAT_TABLE 29*e3ec6ff4SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x800 30*e3ec6ff4SXiaoDong Huang #elif IMAGE_BL1 31*e3ec6ff4SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x440 32*e3ec6ff4SXiaoDong Huang #elif IMAGE_BL2 33*e3ec6ff4SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x400 34*e3ec6ff4SXiaoDong Huang #elif IMAGE_BL31 35*e3ec6ff4SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x800 36*e3ec6ff4SXiaoDong Huang #elif IMAGE_BL32 37*e3ec6ff4SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x440 38*e3ec6ff4SXiaoDong Huang #endif 39*e3ec6ff4SXiaoDong Huang 40*e3ec6ff4SXiaoDong Huang #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 41*e3ec6ff4SXiaoDong Huang 42*e3ec6ff4SXiaoDong Huang #define PLATFORM_SYSTEM_COUNT 1 43*e3ec6ff4SXiaoDong Huang #define PLATFORM_CLUSTER_COUNT 1 44*e3ec6ff4SXiaoDong Huang #define PLATFORM_CLUSTER0_CORE_COUNT 8 45*e3ec6ff4SXiaoDong Huang #define PLATFORM_CLUSTER1_CORE_COUNT 0 46*e3ec6ff4SXiaoDong Huang #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 47*e3ec6ff4SXiaoDong Huang PLATFORM_CLUSTER0_CORE_COUNT) 48*e3ec6ff4SXiaoDong Huang 49*e3ec6ff4SXiaoDong Huang #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 50*e3ec6ff4SXiaoDong Huang PLATFORM_CLUSTER_COUNT + \ 51*e3ec6ff4SXiaoDong Huang PLATFORM_CORE_COUNT) 52*e3ec6ff4SXiaoDong Huang 53*e3ec6ff4SXiaoDong Huang #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 54*e3ec6ff4SXiaoDong Huang 55*e3ec6ff4SXiaoDong Huang #define PLAT_RK_CLST_TO_CPUID_SHIFT 8 56*e3ec6ff4SXiaoDong Huang 57*e3ec6ff4SXiaoDong Huang /* 58*e3ec6ff4SXiaoDong Huang * This macro defines the deepest retention state possible. A higher state 59*e3ec6ff4SXiaoDong Huang * id will represent an invalid or a power down state. 60*e3ec6ff4SXiaoDong Huang */ 61*e3ec6ff4SXiaoDong Huang #define PLAT_MAX_RET_STATE 1 62*e3ec6ff4SXiaoDong Huang 63*e3ec6ff4SXiaoDong Huang /* 64*e3ec6ff4SXiaoDong Huang * This macro defines the deepest power down states possible. Any state ID 65*e3ec6ff4SXiaoDong Huang * higher than this is invalid. 66*e3ec6ff4SXiaoDong Huang */ 67*e3ec6ff4SXiaoDong Huang #define PLAT_MAX_OFF_STATE 2 68*e3ec6ff4SXiaoDong Huang /******************************************************************************* 69*e3ec6ff4SXiaoDong Huang * Platform memory map related constants 70*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 71*e3ec6ff4SXiaoDong Huang /* TF txet, ro, rw, Size: 512KB */ 72*e3ec6ff4SXiaoDong Huang #define TZRAM_BASE (0x0) 73*e3ec6ff4SXiaoDong Huang #define TZRAM_SIZE (0x100000) 74*e3ec6ff4SXiaoDong Huang 75*e3ec6ff4SXiaoDong Huang /******************************************************************************* 76*e3ec6ff4SXiaoDong Huang * BL31 specific defines. 77*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 78*e3ec6ff4SXiaoDong Huang /* 79*e3ec6ff4SXiaoDong Huang * Put BL3-1 at the top of the Trusted RAM 80*e3ec6ff4SXiaoDong Huang */ 81*e3ec6ff4SXiaoDong Huang #define BL31_BASE (TZRAM_BASE + 0x40000) 82*e3ec6ff4SXiaoDong Huang #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 83*e3ec6ff4SXiaoDong Huang 84*e3ec6ff4SXiaoDong Huang /******************************************************************************* 85*e3ec6ff4SXiaoDong Huang * Platform specific page table and MMU setup constants 86*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 87*e3ec6ff4SXiaoDong Huang #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 88*e3ec6ff4SXiaoDong Huang #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 89*e3ec6ff4SXiaoDong Huang 90*e3ec6ff4SXiaoDong Huang #define ADDR_SPACE_SIZE (1ULL << 32) 91*e3ec6ff4SXiaoDong Huang #define MAX_XLAT_TABLES 18 92*e3ec6ff4SXiaoDong Huang #define MAX_MMAP_REGIONS 27 93*e3ec6ff4SXiaoDong Huang 94*e3ec6ff4SXiaoDong Huang /******************************************************************************* 95*e3ec6ff4SXiaoDong Huang * Declarations and constants to access the mailboxes safely. Each mailbox is 96*e3ec6ff4SXiaoDong Huang * aligned on the biggest cache line size in the platform. This is known only 97*e3ec6ff4SXiaoDong Huang * to the platform as it might have a combination of integrated and external 98*e3ec6ff4SXiaoDong Huang * caches. Such alignment ensures that two maiboxes do not sit on the same cache 99*e3ec6ff4SXiaoDong Huang * line at any cache level. They could belong to different cpus/clusters & 100*e3ec6ff4SXiaoDong Huang * get written while being protected by different locks causing corruption of 101*e3ec6ff4SXiaoDong Huang * a valid mailbox address. 102*e3ec6ff4SXiaoDong Huang ******************************************************************************/ 103*e3ec6ff4SXiaoDong Huang #define CACHE_WRITEBACK_SHIFT 6 104*e3ec6ff4SXiaoDong Huang #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 105*e3ec6ff4SXiaoDong Huang 106*e3ec6ff4SXiaoDong Huang /* 107*e3ec6ff4SXiaoDong Huang * Define GICD and GICC and GICR base 108*e3ec6ff4SXiaoDong Huang */ 109*e3ec6ff4SXiaoDong Huang #define PLAT_RK_GICD_BASE PLAT_GICD_BASE 110*e3ec6ff4SXiaoDong Huang #define PLAT_RK_GICC_BASE PLAT_GICC_BASE 111*e3ec6ff4SXiaoDong Huang #define PLAT_RK_GICR_BASE PLAT_GICR_BASE 112*e3ec6ff4SXiaoDong Huang 113*e3ec6ff4SXiaoDong Huang #define PLAT_RK_UART_BASE RK_DBG_UART_BASE 114*e3ec6ff4SXiaoDong Huang #define PLAT_RK_UART_CLOCK RK_DBG_UART_CLOCK 115*e3ec6ff4SXiaoDong Huang #define PLAT_RK_UART_BAUDRATE RK_DBG_UART_BAUDRATE 116*e3ec6ff4SXiaoDong Huang 117*e3ec6ff4SXiaoDong Huang #define PLAT_RK_PRIMARY_CPU 0x0 118*e3ec6ff4SXiaoDong Huang 119*e3ec6ff4SXiaoDong Huang #endif /* __PLATFORM_DEF_H__ */ 120