1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <bl31/bl31.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <drivers/delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <platform.h> 18 #include <platform_def.h> 19 #include <pmu.h> 20 21 #include <plat_private.h> 22 #include <rk3588_clk.h> 23 #include <secure.h> 24 #include <soc.h> 25 26 #define RK3588_DEV_RNG0_BASE 0xf0000000 27 #define RK3588_DEV_RNG0_SIZE 0x0ffff000 28 29 const mmap_region_t plat_rk_mmap[] = { 30 MAP_REGION_FLAT(RK3588_DEV_RNG0_BASE, RK3588_DEV_RNG0_SIZE, 31 MT_DEVICE | MT_RW | MT_SECURE), 32 MAP_REGION_FLAT(DDR_SHARE_MEM, DDR_SHARE_SIZE, 33 MT_DEVICE | MT_RW | MT_NS), 34 { 0 } 35 }; 36 37 /* The RockChip power domain tree descriptor */ 38 const unsigned char rockchip_power_domain_tree_desc[] = { 39 /* No of root nodes */ 40 PLATFORM_SYSTEM_COUNT, 41 /* No of children for the root node */ 42 PLATFORM_CLUSTER_COUNT, 43 /* No of children for the first cluster node */ 44 PLATFORM_CLUSTER0_CORE_COUNT, 45 /* No of children for the second cluster node */ 46 PLATFORM_CLUSTER1_CORE_COUNT 47 }; 48 49 void timer_hp_init(void) 50 { 51 if ((mmio_read_32(TIMER_HP_BASE + TIMER_HP_CTRL) & 0x1) != 0) 52 return; 53 54 mmio_write_32(TIMER_HP_BASE + TIMER_HP_CTRL, 0x0); 55 dsb(); 56 mmio_write_32(TIMER_HP_BASE + TIMER_HP_LOAD_COUNT0, 0xffffffff); 57 mmio_write_32(TIMER_HP_BASE + TIMER_HP_LOAD_COUNT1, 0xffffffff); 58 mmio_write_32(TIMER_HP_BASE + TIMER_HP_INT_EN, 0); 59 dsb(); 60 mmio_write_32(TIMER_HP_BASE + TIMER_HP_CTRL, 0x1); 61 } 62 63 static void system_reset_init(void) 64 { 65 /* enable wdt_ns0~4 trigger global reset and select first reset. 66 * enable tsadc trigger global reset and select first reset. 67 * enable global reset and wdt trigger pmu reset. 68 * select first reset trigger pmu reset.s 69 */ 70 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 0xffdf); 71 72 /* enable wdt_s, wdt_ns reset */ 73 mmio_write_32(BUSSGRF_BASE + SGRF_SOC_CON(2), 0x0c000c00); 74 75 /* reset width = 0xffff */ 76 mmio_write_32(PMU1GRF_BASE + PMU1GRF_SOC_CON(1), 0xffffffff); 77 78 /* enable first/tsadc/wdt reset output */ 79 mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(0), 0x00070007); 80 81 /* pmu1_grf pmu1_ioc hold */ 82 mmio_write_32(PMU1GRF_BASE + PMU1GRF_SOC_CON(7), 0x30003000); 83 84 /* pmu1sgrf hold */ 85 mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(14), 0x00200020); 86 87 /* select tsadc_shut_m0 ionmux*/ 88 mmio_write_32(PMU0IOC_BASE + 0x0, 0x00f00020); 89 } 90 91 void plat_rockchip_soc_init(void) 92 { 93 rockchip_clock_init(); 94 secure_timer_init(); 95 timer_hp_init(); 96 system_reset_init(); 97 sgrf_init(); 98 rockchip_init_scmi_server(); 99 } 100