1 /* 2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <drivers/delay_timer.h> 11 #include <drivers/scmi.h> 12 #include <lib/mmio.h> 13 #include <platform_def.h> 14 15 #include <plat_private.h> 16 #include "rk3588_clk.h" 17 #include <rockchip_sip_svc.h> 18 #include <scmi_clock.h> 19 #include <soc.h> 20 21 enum pll_type_sel { 22 PLL_SEL_AUTO, /* all plls (normal pll or pvtpll) */ 23 PLL_SEL_PVT, 24 PLL_SEL_NOR, 25 PLL_SEL_AUTO_NOR /* all normal plls (apll/gpll/npll) */ 26 }; 27 28 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 29 30 #define RK3588_CPUL_PVTPLL_CON0_L 0x40 31 #define RK3588_CPUL_PVTPLL_CON0_H 0x44 32 #define RK3588_CPUL_PVTPLL_CON1 0x48 33 #define RK3588_CPUL_PVTPLL_CON2 0x4c 34 #define RK3588_CPUB_PVTPLL_CON0_L 0x00 35 #define RK3588_CPUB_PVTPLL_CON0_H 0x04 36 #define RK3588_CPUB_PVTPLL_CON1 0x08 37 #define RK3588_CPUB_PVTPLL_CON2 0x0c 38 #define RK3588_DSU_PVTPLL_CON0_L 0x60 39 #define RK3588_DSU_PVTPLL_CON0_H 0x64 40 #define RK3588_DSU_PVTPLL_CON1 0x70 41 #define RK3588_DSU_PVTPLL_CON2 0x74 42 #define RK3588_GPU_PVTPLL_CON0_L 0x00 43 #define RK3588_GPU_PVTPLL_CON0_H 0x04 44 #define RK3588_GPU_PVTPLL_CON1 0x08 45 #define RK3588_GPU_PVTPLL_CON2 0x0c 46 #define RK3588_NPU_PVTPLL_CON0_L 0x0c 47 #define RK3588_NPU_PVTPLL_CON0_H 0x10 48 #define RK3588_NPU_PVTPLL_CON1 0x14 49 #define RK3588_NPU_PVTPLL_CON2 0x18 50 #define RK3588_PVTPLL_MAX_LENGTH 0x3f 51 52 #define GPLL_RATE 1188000000 53 #define CPLL_RATE 1500000000 54 #define SPLL_RATE 702000000 55 #define AUPLL_RATE 786431952 56 #define NPLL_RATE 850000000 57 58 #define MAX_RATE_TABLE 16 59 60 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) 61 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) 62 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift) 63 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift) 64 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift) 65 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift) 66 67 #define CPU_PLL_PATH_SLOWMODE BITS_WITH_WMASK(0U, 0x3U, 0) 68 #define CPU_PLL_PATH_NORMAL BITS_WITH_WMASK(1U, 0x3U, 0) 69 #define CPU_PLL_PATH_DEEP_SLOW BITS_WITH_WMASK(2U, 0x3U, 0) 70 71 #define CRU_PLL_POWER_DOWN BIT_WITH_WMSK(13) 72 #define CRU_PLL_POWER_UP WMSK_BIT(13) 73 74 /* core_i: from gpll or apll */ 75 #define CLK_CORE_I_SEL_APLL WMSK_BIT(6) 76 #define CLK_CORE_I_SEL_GPLL BIT_WITH_WMSK(6) 77 78 /* clk_core: 79 * from normal pll(core_i: gpll or apll) path or direct pass from apll 80 */ 81 82 /* cpul clk path */ 83 #define CPUL_CLK_PATH_NOR_XIN BITS_WITH_WMASK(0U, 0x3U, 14) 84 #define CPUL_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(1U, 0x3U, 14) 85 #define CPUL_CLK_PATH_NOR_LPLL BITS_WITH_WMASK(2U, 0x3U, 14) 86 87 #define CPUL_CLK_PATH_LPLL (BITS_WITH_WMASK(0U, 0x3U, 5) | \ 88 BITS_WITH_WMASK(0U, 0x3U, 12)) 89 #define CPUL_CLK_PATH_DIR_LPLL (BITS_WITH_WMASK(0x1, 0x3U, 5) | \ 90 BITS_WITH_WMASK(1U, 0x3U, 12)) 91 #define CPUL_CLK_PATH_PVTPLL (BITS_WITH_WMASK(0x2, 0x3U, 5) | \ 92 BITS_WITH_WMASK(2U, 0x3U, 12)) 93 94 #define CPUL_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 14) 95 #define CPUL_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 14) 96 97 /* cpub01 clk path */ 98 #define CPUB01_CLK_PATH_NOR_XIN BITS_WITH_WMASK(0U, 0x3U, 6) 99 #define CPUB01_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(1U, 0x3U, 6) 100 #define CPUB01_CLK_PATH_NOR_B0PLL BITS_WITH_WMASK(2U, 0x3U, 6) 101 102 #define CPUB01_CLK_PATH_B0PLL BITS_WITH_WMASK(0U, 0x3U, 13) 103 #define CPUB01_CLK_PATH_DIR_B0PLL BITS_WITH_WMASK(1U, 0x3U, 13) 104 #define CPUB01_CLK_PATH_B0_PVTPLL BITS_WITH_WMASK(2U, 0x3U, 13) 105 106 #define CPUB01_CLK_PATH_B1PLL BITS_WITH_WMASK(0U, 0x3U, 5) 107 #define CPUB01_CLK_PATH_DIR_B1PLL BITS_WITH_WMASK(1U, 0x3U, 5) 108 #define CPUB01_CLK_PATH_B1_PVTPLL BITS_WITH_WMASK(2U, 0x3U, 5) 109 110 #define CPUB01_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 2) 111 #define CPUB01_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 2) 112 113 #define CPUB_PCLK_PATH_100M BITS_WITH_WMASK(0U, 0x3U, 0) 114 #define CPUB_PCLK_PATH_50M BITS_WITH_WMASK(1U, 0x3U, 0) 115 #define CPUB_PCLK_PATH_24M BITS_WITH_WMASK(2U, 0x3U, 0) 116 117 /* dsu clk path */ 118 #define SCLK_DSU_PATH_NOR_B0PLL BITS_WITH_WMASK(0U, 0x3U, 12) 119 #define SCLK_DSU_PATH_NOR_B1PLL BITS_WITH_WMASK(1U, 0x3U, 12) 120 #define SCLK_DSU_PATH_NOR_LPLL BITS_WITH_WMASK(2U, 0x3U, 12) 121 #define SCLK_DSU_PATH_NOR_GPLL BITS_WITH_WMASK(3U, 0x3U, 12) 122 123 #define DSU_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 15) 124 #define DSU_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 15) 125 126 #define SCLK_DSU_PATH_NOR_PLL WMSK_BIT(0) 127 #define SCLK_DSU_PATH_PVTPLL BIT_WITH_WMSK(0) 128 129 /* npu clk path */ 130 #define NPU_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(0U, 0x7U, 7) 131 #define NPU_CLK_PATH_NOR_CPLL BITS_WITH_WMASK(1U, 0x7U, 7) 132 #define NPU_CLK_PATH_NOR_AUPLL BITS_WITH_WMASK(2U, 0x7U, 7) 133 #define NPU_CLK_PATH_NOR_NPLL BITS_WITH_WMASK(3U, 0x7U, 7) 134 #define NPU_CLK_PATH_NOR_SPLL BITS_WITH_WMASK(4U, 0x7U, 7) 135 136 #define NPU_CLK_PATH_NOR_PLL WMSK_BIT(0) 137 #define NPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(0) 138 139 /* gpu clk path */ 140 #define GPU_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(0U, 0x7U, 5) 141 #define GPU_CLK_PATH_NOR_CPLL BITS_WITH_WMASK(1U, 0x7U, 5) 142 #define GPU_CLK_PATH_NOR_AUPLL BITS_WITH_WMASK(2U, 0x7U, 5) 143 #define GPU_CLK_PATH_NOR_NPLL BITS_WITH_WMASK(3U, 0x7U, 5) 144 #define GPU_CLK_PATH_NOR_SPLL BITS_WITH_WMASK(4U, 0x7U, 5) 145 #define GPU_CLK_PATH_NOR_PLL WMSK_BIT(14) 146 #define GPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(14) 147 148 #define PVTPLL_NEED(type, length) (((type) == PLL_SEL_PVT || \ 149 (type) == PLL_SEL_AUTO) && \ 150 (length)) 151 152 struct pvtpll_table { 153 unsigned int rate; 154 uint32_t length; 155 uint32_t ring_sel; 156 }; 157 158 struct sys_clk_info_t { 159 struct pvtpll_table *cpul_table; 160 struct pvtpll_table *cpub01_table; 161 struct pvtpll_table *cpub23_table; 162 struct pvtpll_table *gpu_table; 163 struct pvtpll_table *npu_table; 164 unsigned int cpul_rate_count; 165 unsigned int cpub01_rate_count; 166 unsigned int cpub23_rate_count; 167 unsigned int gpu_rate_count; 168 unsigned int npu_rate_count; 169 unsigned long cpul_rate; 170 unsigned long dsu_rate; 171 unsigned long cpub01_rate; 172 unsigned long cpub23_rate; 173 unsigned long gpu_rate; 174 unsigned long npu_rate; 175 }; 176 177 #define RK3588_SCMI_CLOCK(_id, _name, _data, _table, _cnt, _is_s) \ 178 { \ 179 .id = _id, \ 180 .name = _name, \ 181 .clk_ops = _data, \ 182 .rate_table = _table, \ 183 .rate_cnt = _cnt, \ 184 .is_security = _is_s, \ 185 } 186 187 #define ROCKCHIP_PVTPLL(_rate, _sel, _len) \ 188 { \ 189 .rate = _rate##U, \ 190 .ring_sel = _sel, \ 191 .length = _len, \ 192 } 193 194 static struct pvtpll_table rk3588_cpul_pvtpll_table[] = { 195 /* rate_hz, ring_sel, length */ 196 ROCKCHIP_PVTPLL(1800000000, 1, 15), 197 ROCKCHIP_PVTPLL(1704000000, 1, 15), 198 ROCKCHIP_PVTPLL(1608000000, 1, 15), 199 ROCKCHIP_PVTPLL(1416000000, 1, 15), 200 ROCKCHIP_PVTPLL(1200000000, 1, 17), 201 ROCKCHIP_PVTPLL(1008000000, 1, 22), 202 ROCKCHIP_PVTPLL(816000000, 1, 32), 203 ROCKCHIP_PVTPLL(600000000, 0, 0), 204 ROCKCHIP_PVTPLL(408000000, 0, 0), 205 { /* sentinel */ }, 206 }; 207 208 static struct pvtpll_table rk3588_cpub0_pvtpll_table[] = { 209 /* rate_hz, ring_sel, length */ 210 ROCKCHIP_PVTPLL(2400000000, 1, 11), 211 ROCKCHIP_PVTPLL(2352000000, 1, 11), 212 ROCKCHIP_PVTPLL(2304000000, 1, 11), 213 ROCKCHIP_PVTPLL(2256000000, 1, 11), 214 ROCKCHIP_PVTPLL(2208000000, 1, 11), 215 ROCKCHIP_PVTPLL(2112000000, 1, 11), 216 ROCKCHIP_PVTPLL(2016000000, 1, 11), 217 ROCKCHIP_PVTPLL(1800000000, 1, 11), 218 ROCKCHIP_PVTPLL(1608000000, 1, 11), 219 ROCKCHIP_PVTPLL(1416000000, 1, 13), 220 ROCKCHIP_PVTPLL(1200000000, 1, 17), 221 ROCKCHIP_PVTPLL(1008000000, 1, 23), 222 ROCKCHIP_PVTPLL(816000000, 1, 33), 223 ROCKCHIP_PVTPLL(600000000, 0, 0), 224 ROCKCHIP_PVTPLL(408000000, 0, 0), 225 { /* sentinel */ }, 226 }; 227 228 static struct 229 pvtpll_table rk3588_cpub1_pvtpll_table[ARRAY_SIZE(rk3588_cpub0_pvtpll_table)] = { 0 }; 230 231 static struct pvtpll_table rk3588_gpu_pvtpll_table[] = { 232 /* rate_hz, ring_sel, length */ 233 ROCKCHIP_PVTPLL(1000000000, 1, 12), 234 ROCKCHIP_PVTPLL(900000000, 1, 12), 235 ROCKCHIP_PVTPLL(800000000, 1, 12), 236 ROCKCHIP_PVTPLL(700000000, 1, 13), 237 ROCKCHIP_PVTPLL(600000000, 1, 17), 238 ROCKCHIP_PVTPLL(500000000, 1, 25), 239 ROCKCHIP_PVTPLL(400000000, 1, 38), 240 ROCKCHIP_PVTPLL(300000000, 1, 55), 241 ROCKCHIP_PVTPLL(200000000, 0, 0), 242 { /* sentinel */ }, 243 }; 244 245 static struct pvtpll_table rk3588_npu_pvtpll_table[] = { 246 /* rate_hz, ring_sel, length */ 247 ROCKCHIP_PVTPLL(1000000000, 1, 12), 248 ROCKCHIP_PVTPLL(900000000, 1, 12), 249 ROCKCHIP_PVTPLL(800000000, 1, 12), 250 ROCKCHIP_PVTPLL(700000000, 1, 13), 251 ROCKCHIP_PVTPLL(600000000, 1, 17), 252 ROCKCHIP_PVTPLL(500000000, 1, 25), 253 ROCKCHIP_PVTPLL(400000000, 1, 38), 254 ROCKCHIP_PVTPLL(300000000, 1, 55), 255 ROCKCHIP_PVTPLL(200000000, 0, 0), 256 { /* sentinel */ }, 257 }; 258 259 static unsigned long rk3588_cpul_rates[] = { 260 408000000, 600000000, 816000000, 1008000000, 261 1200000000, 1416000000, 1608000000, 1800000063, 262 }; 263 264 static unsigned long rk3588_cpub_rates[] = { 265 408000000, 816000000, 1008000000, 1200000000, 266 1416000000, 1608000000, 1800000000, 2016000000, 267 2208000000, 2304000000, 2400000063 268 }; 269 270 static unsigned long rk3588_gpu_rates[] = { 271 200000000, 300000000, 400000000, 500000000, 272 600000000, 700000000, 800000000, 900000000, 273 1000000063 274 }; 275 276 static unsigned long rk3588_sbus_rates[] = { 277 24000000, 50000000, 100000000, 150000000, 200000000, 278 250000000, 350000000, 700000000 279 }; 280 281 static unsigned long rk3588_sdmmc_rates[] = { 282 400000, 24000000, 50000000, 100000000, 150000000, 200000000, 283 300000000, 400000000, 600000000, 700000000 284 }; 285 286 static struct sys_clk_info_t sys_clk_info; 287 static int clk_scmi_dsu_set_rate(rk_scmi_clock_t *clock, unsigned long rate); 288 289 static struct pvtpll_table *rkclk_get_pvtpll_config(struct pvtpll_table *table, 290 unsigned int count, 291 unsigned int freq_hz) 292 { 293 int i; 294 295 for (i = 0; i < count; i++) { 296 if (freq_hz == table[i].rate) 297 return &table[i]; 298 } 299 return NULL; 300 } 301 302 static int clk_cpul_set_rate(unsigned long rate, enum pll_type_sel type) 303 { 304 struct pvtpll_table *pvtpll; 305 int div; 306 307 if (rate == 0) 308 return SCMI_INVALID_PARAMETERS; 309 310 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpul_table, 311 sys_clk_info.cpul_rate_count, rate); 312 if (pvtpll == NULL) 313 return SCMI_INVALID_PARAMETERS; 314 315 /* set lpll */ 316 if (PVTPLL_NEED(type, pvtpll->length) != 0) { 317 /* set clock gating interval */ 318 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON2, 319 0x00040000); 320 /* set ring sel */ 321 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, 322 0x07000000 | (pvtpll->ring_sel << 8)); 323 /* set length */ 324 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_H, 325 0x003f0000 | pvtpll->length); 326 /* set cal cnt = 24, T = 1us */ 327 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON1, 328 0x18); 329 /* enable pvtpll */ 330 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, 331 0x00020002); 332 /* start monitor */ 333 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L, 334 0x00010001); 335 /* set corel mux pvtpll */ 336 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), 337 CPUL_PVTPLL_PATH_PVTPLL); 338 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), 339 CPUL_CLK_PATH_PVTPLL); 340 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), 341 CPUL_CLK_PATH_PVTPLL); 342 return 0; 343 } 344 345 /* set clk corel div */ 346 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; 347 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), 348 CLKDIV_5BITS_SHF(div, 0) | CLKDIV_5BITS_SHF(div, 7)); 349 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), 350 CLKDIV_5BITS_SHF(div, 0) | CLKDIV_5BITS_SHF(div, 7)); 351 /* set corel mux gpll */ 352 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), 353 CPUL_CLK_PATH_NOR_GPLL); 354 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), 355 CPUL_CLK_PATH_LPLL); 356 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), 357 CPUL_CLK_PATH_LPLL); 358 359 return 0; 360 } 361 362 static int clk_scmi_cpul_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 363 { 364 int ret; 365 366 if (rate == 0) 367 return SCMI_INVALID_PARAMETERS; 368 369 ret = clk_cpul_set_rate(rate, PLL_SEL_AUTO); 370 if (ret == 0) { 371 sys_clk_info.cpul_rate = rate; 372 ret = clk_scmi_dsu_set_rate(clock, rate); 373 } 374 375 return ret; 376 } 377 378 static unsigned long rk3588_lpll_get_rate(void) 379 { 380 unsigned int m, p, s, k; 381 uint64_t rate64 = 24000000, postdiv; 382 int mode; 383 384 mode = (mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) >> 14) & 385 0x3; 386 387 if (mode == 0) 388 return rate64; 389 390 m = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(16)) >> 391 CRU_PLLCON0_M_SHIFT) & 392 CRU_PLLCON0_M_MASK; 393 p = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >> 394 CRU_PLLCON1_P_SHIFT) & 395 CRU_PLLCON1_P_MASK; 396 s = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >> 397 CRU_PLLCON1_S_SHIFT) & 398 CRU_PLLCON1_S_MASK; 399 k = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(18)) >> 400 CRU_PLLCON2_K_SHIFT) & 401 CRU_PLLCON2_K_MASK; 402 403 rate64 *= m; 404 rate64 = rate64 / p; 405 406 if (k != 0) { 407 /* fractional mode */ 408 uint64_t frac_rate64 = 24000000 * k; 409 410 postdiv = p * 65535; 411 frac_rate64 = frac_rate64 / postdiv; 412 rate64 += frac_rate64; 413 } 414 rate64 = rate64 >> s; 415 416 return (unsigned long)rate64; 417 } 418 419 static unsigned long clk_scmi_cpul_get_rate(rk_scmi_clock_t *clock) 420 { 421 int src, div; 422 423 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x0060; 424 src = src >> 5; 425 if (src == 2) { 426 return sys_clk_info.cpul_rate; 427 } else { 428 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) & 0xc000; 429 src = src >> 14; 430 div = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x1f; 431 switch (src) { 432 case 0: 433 return 24000000; 434 case 1: 435 /* Make the return rate is equal to the set rate */ 436 if (sys_clk_info.cpul_rate) 437 return sys_clk_info.cpul_rate; 438 else 439 return GPLL_RATE / (div + 1); 440 case 2: 441 return rk3588_lpll_get_rate(); 442 default: 443 return 0; 444 } 445 } 446 } 447 448 static int clk_scmi_cpul_set_status(rk_scmi_clock_t *clock, bool status) 449 { 450 return 0; 451 } 452 453 static void clk_scmi_b0pll_disable(void) 454 { 455 static bool is_b0pll_disabled; 456 457 if (is_b0pll_disabled != 0) 458 return; 459 460 /* set coreb01 mux gpll */ 461 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), 462 CPUB01_CLK_PATH_NOR_GPLL); 463 /* pll enter slow mode */ 464 mmio_write_32(BIGCORE0CRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE); 465 /* set pll power down */ 466 mmio_write_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1), CRU_PLL_POWER_DOWN); 467 468 is_b0pll_disabled = true; 469 } 470 471 static int clk_cpub01_set_rate(unsigned long rate, enum pll_type_sel type) 472 { 473 struct pvtpll_table *pvtpll; 474 int div; 475 476 if (rate == 0) 477 return SCMI_INVALID_PARAMETERS; 478 479 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpub01_table, 480 sys_clk_info.cpub01_rate_count, rate); 481 if (pvtpll == NULL) 482 return SCMI_INVALID_PARAMETERS; 483 484 /* set b0pll */ 485 if (PVTPLL_NEED(type, pvtpll->length)) { 486 /* set clock gating interval */ 487 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON2, 488 0x00040000); 489 /* set ring sel */ 490 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, 491 0x07000000 | (pvtpll->ring_sel << 8)); 492 /* set length */ 493 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_H, 494 0x003f0000 | pvtpll->length); 495 /* set cal cnt = 24, T = 1us */ 496 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON1, 497 0x18); 498 /* enable pvtpll */ 499 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, 500 0x00020002); 501 /* start monitor */ 502 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, 503 0x00010001); 504 /* set core mux pvtpll */ 505 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), 506 CPUB01_PVTPLL_PATH_PVTPLL); 507 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), 508 CPUB01_CLK_PATH_B0_PVTPLL); 509 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1), 510 CPUB01_CLK_PATH_B1_PVTPLL); 511 goto out; 512 } 513 514 /* set clk coreb01 div */ 515 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; 516 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), 517 CLKDIV_5BITS_SHF(div, 8)); 518 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1), 519 CLKDIV_5BITS_SHF(div, 0)); 520 /* set coreb01 mux gpll */ 521 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), 522 CPUB01_CLK_PATH_NOR_GPLL); 523 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), 524 CPUB01_CLK_PATH_B0PLL); 525 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1), 526 CPUB01_CLK_PATH_B1PLL); 527 528 out: 529 clk_scmi_b0pll_disable(); 530 531 return 0; 532 } 533 534 static int clk_scmi_cpub01_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 535 { 536 int ret; 537 538 if (rate == 0) 539 return SCMI_INVALID_PARAMETERS; 540 541 ret = clk_cpub01_set_rate(rate, PLL_SEL_AUTO); 542 if (ret == 0) 543 sys_clk_info.cpub01_rate = rate; 544 545 return ret; 546 } 547 548 static unsigned long rk3588_b0pll_get_rate(void) 549 { 550 unsigned int m, p, s, k; 551 uint64_t rate64 = 24000000, postdiv; 552 int mode; 553 554 mode = (mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0)) >> 6) & 555 0x3; 556 557 if (mode == 0) 558 return rate64; 559 560 m = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(0)) >> 561 CRU_PLLCON0_M_SHIFT) & 562 CRU_PLLCON0_M_MASK; 563 p = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1)) >> 564 CRU_PLLCON1_P_SHIFT) & 565 CRU_PLLCON1_P_MASK; 566 s = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1)) >> 567 CRU_PLLCON1_S_SHIFT) & 568 CRU_PLLCON1_S_MASK; 569 k = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(2)) >> 570 CRU_PLLCON2_K_SHIFT) & 571 CRU_PLLCON2_K_MASK; 572 573 rate64 *= m; 574 rate64 = rate64 / p; 575 576 if (k != 0) { 577 /* fractional mode */ 578 uint64_t frac_rate64 = 24000000 * k; 579 580 postdiv = p * 65535; 581 frac_rate64 = frac_rate64 / postdiv; 582 rate64 += frac_rate64; 583 } 584 rate64 = rate64 >> s; 585 586 return (unsigned long)rate64; 587 } 588 589 static unsigned long clk_scmi_cpub01_get_rate(rk_scmi_clock_t *clock) 590 { 591 int value, src, div; 592 593 value = mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0)); 594 src = (value & 0x6000) >> 13; 595 if (src == 2) { 596 return sys_clk_info.cpub01_rate; 597 } else { 598 src = (value & 0x00c0) >> 6; 599 div = (value & 0x1f00) >> 8; 600 switch (src) { 601 case 0: 602 return 24000000; 603 case 1: 604 /* Make the return rate is equal to the set rate */ 605 if (sys_clk_info.cpub01_rate) 606 return sys_clk_info.cpub01_rate; 607 else 608 return GPLL_RATE / (div + 1); 609 case 2: 610 return rk3588_b0pll_get_rate(); 611 default: 612 return 0; 613 } 614 } 615 } 616 617 static int clk_scmi_cpub01_set_status(rk_scmi_clock_t *clock, bool status) 618 { 619 return 0; 620 } 621 622 static void clk_scmi_b1pll_disable(void) 623 { 624 static bool is_b1pll_disabled; 625 626 if (is_b1pll_disabled != 0) 627 return; 628 629 /* set coreb23 mux gpll */ 630 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), 631 CPUB01_CLK_PATH_NOR_GPLL); 632 /* pll enter slow mode */ 633 mmio_write_32(BIGCORE1CRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE); 634 /* set pll power down */ 635 mmio_write_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9), CRU_PLL_POWER_DOWN); 636 637 is_b1pll_disabled = true; 638 } 639 640 static int clk_cpub23_set_rate(unsigned long rate, enum pll_type_sel type) 641 { 642 struct pvtpll_table *pvtpll; 643 int div; 644 645 if (rate == 0) 646 return SCMI_INVALID_PARAMETERS; 647 648 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpub23_table, 649 sys_clk_info.cpub23_rate_count, rate); 650 if (pvtpll == NULL) 651 return SCMI_INVALID_PARAMETERS; 652 653 /* set b1pll */ 654 if (PVTPLL_NEED(type, pvtpll->length)) { 655 /* set clock gating interval */ 656 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON2, 657 0x00040000); 658 /* set ring sel */ 659 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, 660 0x07000000 | (pvtpll->ring_sel << 8)); 661 /* set length */ 662 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_H, 663 0x003f0000 | pvtpll->length); 664 /* set cal cnt = 24, T = 1us */ 665 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON1, 666 0x18); 667 /* enable pvtpll */ 668 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, 669 0x00020002); 670 /* start monitor */ 671 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L, 672 0x00010001); 673 /* set core mux pvtpll */ 674 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), 675 CPUB01_PVTPLL_PATH_PVTPLL); 676 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), 677 CPUB01_CLK_PATH_B0_PVTPLL); 678 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1), 679 CPUB01_CLK_PATH_B1_PVTPLL); 680 goto out; 681 } 682 683 /* set clk coreb23 div */ 684 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; 685 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), 686 CLKDIV_5BITS_SHF(div, 8)); 687 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1), 688 CLKDIV_5BITS_SHF(div, 0)); 689 /* set coreb23 mux gpll */ 690 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), 691 CPUB01_CLK_PATH_NOR_GPLL); 692 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), 693 CPUB01_CLK_PATH_B0PLL); 694 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1), 695 CPUB01_CLK_PATH_B1PLL); 696 697 out: 698 clk_scmi_b1pll_disable(); 699 700 return 0; 701 } 702 703 static int clk_scmi_cpub23_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 704 { 705 int ret; 706 707 if (rate == 0) 708 return SCMI_INVALID_PARAMETERS; 709 710 ret = clk_cpub23_set_rate(rate, PLL_SEL_AUTO); 711 if (ret == 0) 712 sys_clk_info.cpub23_rate = rate; 713 714 return ret; 715 } 716 717 static unsigned long rk3588_b1pll_get_rate(void) 718 { 719 unsigned int m, p, s, k; 720 uint64_t rate64 = 24000000, postdiv; 721 int mode; 722 723 mode = (mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0)) >> 6) & 724 0x3; 725 726 if (mode == 0) 727 return rate64; 728 729 m = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(8)) >> 730 CRU_PLLCON0_M_SHIFT) & 731 CRU_PLLCON0_M_MASK; 732 p = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9)) >> 733 CRU_PLLCON1_P_SHIFT) & 734 CRU_PLLCON1_P_MASK; 735 s = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9)) >> 736 CRU_PLLCON1_S_SHIFT) & 737 CRU_PLLCON1_S_MASK; 738 k = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(10)) >> 739 CRU_PLLCON2_K_SHIFT) & 740 CRU_PLLCON2_K_MASK; 741 742 rate64 *= m; 743 rate64 = rate64 / p; 744 745 if (k != 0) { 746 /* fractional mode */ 747 uint64_t frac_rate64 = 24000000 * k; 748 749 postdiv = p * 65535; 750 frac_rate64 = frac_rate64 / postdiv; 751 rate64 += frac_rate64; 752 } 753 rate64 = rate64 >> s; 754 755 return (unsigned long)rate64; 756 } 757 758 static unsigned long clk_scmi_cpub23_get_rate(rk_scmi_clock_t *clock) 759 { 760 int value, src, div; 761 762 value = mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0)); 763 src = (value & 0x6000) >> 13; 764 if (src == 2) { 765 return sys_clk_info.cpub23_rate; 766 } else { 767 src = (value & 0x00c0) >> 6; 768 div = (value & 0x1f00) >> 8; 769 switch (src) { 770 case 0: 771 return 24000000; 772 case 1: 773 /* Make the return rate is equal to the set rate */ 774 if (sys_clk_info.cpub23_rate) 775 return sys_clk_info.cpub23_rate; 776 else 777 return GPLL_RATE / (div + 1); 778 case 2: 779 return rk3588_b1pll_get_rate(); 780 default: 781 return 0; 782 } 783 } 784 } 785 786 static int clk_scmi_cpub23_set_status(rk_scmi_clock_t *clock, bool status) 787 { 788 return 0; 789 } 790 791 static unsigned long clk_scmi_dsu_get_rate(rk_scmi_clock_t *clock) 792 { 793 int src, div; 794 795 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(1)) & 0x1; 796 if (src != 0) { 797 return sys_clk_info.dsu_rate; 798 } else { 799 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(0)) & 0x3000; 800 src = src >> 12; 801 div = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(0)) & 0xf80; 802 div = div >> 7; 803 switch (src) { 804 case 0: 805 return rk3588_b0pll_get_rate() / (div + 1); 806 case 1: 807 return rk3588_b1pll_get_rate() / (div + 1); 808 case 2: 809 return rk3588_lpll_get_rate() / (div + 1); 810 case 3: 811 return GPLL_RATE / (div + 1); 812 default: 813 return 0; 814 } 815 } 816 } 817 818 static void clk_scmi_lpll_disable(void) 819 { 820 static bool is_lpll_disabled; 821 822 if (is_lpll_disabled) 823 return; 824 825 /* set corel mux gpll */ 826 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), 827 CPUL_CLK_PATH_NOR_GPLL); 828 /* set dsu mux gpll */ 829 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0), 830 SCLK_DSU_PATH_NOR_GPLL); 831 /* pll enter slow mode */ 832 mmio_write_32(DSUCRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE); 833 /* set pll power down */ 834 mmio_write_32(DSUCRU_BASE + CRU_PLL_CON(17), CRU_PLL_POWER_DOWN); 835 836 is_lpll_disabled = true; 837 } 838 839 static int clk_dsu_set_rate(unsigned long rate, enum pll_type_sel type) 840 { 841 struct pvtpll_table *pvtpll; 842 int div; 843 844 if (rate == 0) 845 return SCMI_INVALID_PARAMETERS; 846 847 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpul_table, 848 sys_clk_info.cpul_rate_count, rate); 849 if (pvtpll == NULL) 850 return SCMI_INVALID_PARAMETERS; 851 852 /* set pvtpll */ 853 if (PVTPLL_NEED(type, pvtpll->length)) { 854 /* set clock gating interval */ 855 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON2, 856 0x00040000); 857 /* set ring sel */ 858 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, 859 0x07000000 | (pvtpll->ring_sel << 8)); 860 /* set length */ 861 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_H, 862 0x003f0000 | pvtpll->length); 863 /* set cal cnt = 24, T = 1us */ 864 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON1, 865 0x18); 866 /* enable pvtpll */ 867 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, 868 0x00020002); 869 /* start monitor */ 870 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L, 871 0x00010001); 872 /* set dsu mux pvtpll */ 873 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), 874 DSU_PVTPLL_PATH_PVTPLL); 875 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(1), 876 SCLK_DSU_PATH_PVTPLL); 877 goto out; 878 } 879 /* set dsu div */ 880 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1; 881 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0), 882 CLKDIV_5BITS_SHF(div, 7)); 883 /* set dsu mux gpll */ 884 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0), 885 SCLK_DSU_PATH_NOR_GPLL); 886 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(1), 887 SCLK_DSU_PATH_NOR_PLL); 888 889 out: 890 clk_scmi_lpll_disable(); 891 892 return 0; 893 } 894 895 static int clk_scmi_dsu_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 896 { 897 int ret; 898 899 if (rate == 0) 900 return SCMI_INVALID_PARAMETERS; 901 902 ret = clk_dsu_set_rate(rate, PLL_SEL_AUTO); 903 904 if (ret == 0) 905 sys_clk_info.dsu_rate = rate; 906 return ret; 907 } 908 909 static int clk_scmi_dsu_set_status(rk_scmi_clock_t *clock, bool status) 910 { 911 return 0; 912 } 913 914 static unsigned long clk_scmi_gpu_get_rate(rk_scmi_clock_t *clock) 915 { 916 int div, src; 917 918 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x4000) != 0) { 919 return sys_clk_info.gpu_rate; 920 } else { 921 div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x1f; 922 src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x00e0; 923 src = src >> 5; 924 switch (src) { 925 case 0: 926 /* Make the return rate is equal to the set rate */ 927 if (sys_clk_info.gpu_rate) 928 return sys_clk_info.gpu_rate; 929 else 930 return GPLL_RATE / (div + 1); 931 case 1: 932 return CPLL_RATE / (div + 1); 933 case 2: 934 return AUPLL_RATE / (div + 1); 935 case 3: 936 return NPLL_RATE / (div + 1); 937 case 4: 938 return SPLL_RATE / (div + 1); 939 default: 940 return 0; 941 } 942 } 943 } 944 945 static int clk_gpu_set_rate(unsigned long rate, enum pll_type_sel type) 946 { 947 struct pvtpll_table *pvtpll; 948 int div; 949 950 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.gpu_table, 951 sys_clk_info.gpu_rate_count, rate); 952 if (pvtpll == NULL) 953 return SCMI_INVALID_PARAMETERS; 954 955 if (PVTPLL_NEED(type, pvtpll->length)) { 956 /* set clock gating interval */ 957 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON2, 958 0x00040000); 959 /* set ring sel */ 960 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L, 961 0x07000000 | (pvtpll->ring_sel << 8)); 962 /* set length */ 963 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_H, 964 0x003f0000 | pvtpll->length); 965 /* set cal cnt = 24, T = 1us */ 966 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON1, 967 0x18); 968 /* enable pvtpll */ 969 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L, 970 0x00020002); 971 /* start monitor */ 972 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L, 973 0x00010001); 974 /* set gpu mux pvtpll */ 975 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), 976 GPU_CLK_PATH_PVTPLL); 977 return 0; 978 } 979 980 /* set gpu div */ 981 div = DIV_ROUND_UP(GPLL_RATE, rate); 982 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), 983 CLKDIV_5BITS_SHF(div - 1, 0)); 984 /* set gpu mux gpll */ 985 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), 986 GPU_CLK_PATH_NOR_GPLL); 987 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), 988 GPU_CLK_PATH_NOR_PLL); 989 990 return 0; 991 } 992 993 static int clk_scmi_gpu_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 994 { 995 int ret; 996 997 if (rate == 0) 998 return SCMI_INVALID_PARAMETERS; 999 1000 ret = clk_gpu_set_rate(rate, PLL_SEL_AUTO); 1001 if (ret == 0) 1002 sys_clk_info.gpu_rate = rate; 1003 1004 return ret; 1005 } 1006 1007 static int clk_scmi_gpu_set_status(rk_scmi_clock_t *clock, bool status) 1008 { 1009 return 0; 1010 } 1011 1012 static unsigned long clk_scmi_npu_get_rate(rk_scmi_clock_t *clock) 1013 { 1014 int div, src; 1015 1016 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(74)) & 0x1) != 0) { 1017 return sys_clk_info.npu_rate; 1018 } else { 1019 div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(73)) & 0x007c; 1020 div = div >> 2; 1021 src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(73)) & 0x0380; 1022 src = src >> 7; 1023 switch (src) { 1024 case 0: 1025 /* Make the return rate is equal to the set rate */ 1026 if (sys_clk_info.npu_rate != 0) 1027 return sys_clk_info.npu_rate; 1028 else 1029 return GPLL_RATE / (div + 1); 1030 case 1: 1031 return CPLL_RATE / (div + 1); 1032 case 2: 1033 return AUPLL_RATE / (div + 1); 1034 case 3: 1035 return NPLL_RATE / (div + 1); 1036 case 4: 1037 return SPLL_RATE / (div + 1); 1038 default: 1039 return 0; 1040 } 1041 } 1042 } 1043 1044 static int clk_npu_set_rate(unsigned long rate, enum pll_type_sel type) 1045 { 1046 struct pvtpll_table *pvtpll; 1047 int div; 1048 1049 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.npu_table, 1050 sys_clk_info.npu_rate_count, rate); 1051 if (pvtpll == NULL) 1052 return SCMI_INVALID_PARAMETERS; 1053 1054 if (PVTPLL_NEED(type, pvtpll->length)) { 1055 /* set clock gating interval */ 1056 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON2, 1057 0x00040000); 1058 /* set ring sel */ 1059 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L, 1060 0x07000000 | (pvtpll->ring_sel << 8)); 1061 /* set length */ 1062 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_H, 1063 0x003f0000 | pvtpll->length); 1064 /* set cal cnt = 24, T = 1us */ 1065 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON1, 1066 0x18); 1067 /* enable pvtpll */ 1068 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L, 1069 0x00020002); 1070 /* start monitor */ 1071 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L, 1072 0x00010001); 1073 /* set npu mux pvtpll */ 1074 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(74), 1075 NPU_CLK_PATH_PVTPLL); 1076 return 0; 1077 } 1078 1079 /* set npu div */ 1080 div = DIV_ROUND_UP(GPLL_RATE, rate); 1081 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(73), 1082 CLKDIV_5BITS_SHF(div - 1, 2)); 1083 /* set npu mux gpll */ 1084 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(73), 1085 NPU_CLK_PATH_NOR_GPLL); 1086 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(74), 1087 NPU_CLK_PATH_NOR_PLL); 1088 1089 return 0; 1090 } 1091 1092 static int clk_scmi_npu_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1093 { 1094 int ret; 1095 1096 if (rate == 0) 1097 return SCMI_INVALID_PARAMETERS; 1098 1099 ret = clk_npu_set_rate(rate, PLL_SEL_AUTO); 1100 if (ret == 0) 1101 sys_clk_info.npu_rate = rate; 1102 1103 return ret; 1104 } 1105 1106 static int clk_scmi_npu_set_status(rk_scmi_clock_t *clock, bool status) 1107 { 1108 return 0; 1109 } 1110 1111 static unsigned long clk_scmi_sbus_get_rate(rk_scmi_clock_t *clock) 1112 { 1113 int div; 1114 1115 if ((mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)) & 0x0800) != 0) { 1116 div = mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)); 1117 div = (div & 0x03e0) >> 5; 1118 return SPLL_RATE / (div + 1); 1119 } else { 1120 return OSC_HZ; 1121 } 1122 } 1123 1124 static int clk_scmi_sbus_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1125 { 1126 int div; 1127 1128 if (rate == OSC_HZ) { 1129 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), 1130 WMSK_BIT(11)); 1131 return 0; 1132 } 1133 1134 div = DIV_ROUND_UP(SPLL_RATE, rate); 1135 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), 1136 CLKDIV_5BITS_SHF(div - 1, 5)); 1137 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), 1138 BIT_WITH_WMSK(11) | WMSK_BIT(10)); 1139 return 0; 1140 } 1141 1142 static int clk_scmi_sbus_set_status(rk_scmi_clock_t *clock, bool status) 1143 { 1144 return 0; 1145 } 1146 1147 static unsigned long clk_scmi_pclk_sbus_get_rate(rk_scmi_clock_t *clock) 1148 { 1149 int div; 1150 1151 div = mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)); 1152 div = div & 0x001f; 1153 return SPLL_RATE / (div + 1); 1154 1155 } 1156 1157 static int clk_scmi_pclk_sbus_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1158 { 1159 int div; 1160 1161 div = DIV_ROUND_UP(SPLL_RATE, rate); 1162 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0), 1163 CLKDIV_5BITS_SHF(div - 1, 0)); 1164 return 0; 1165 } 1166 1167 static int clk_scmi_pclk_sbus_set_status(rk_scmi_clock_t *clock, bool status) 1168 { 1169 return 0; 1170 } 1171 1172 static unsigned long clk_scmi_cclk_sdmmc_get_rate(rk_scmi_clock_t *clock) 1173 { 1174 int div; 1175 uint32_t src; 1176 1177 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x3000; 1178 src = src >> 12; 1179 div = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x0fc0; 1180 div = div >> 6; 1181 if (src == 1) { 1182 return SPLL_RATE / (div + 1); 1183 } else if (src == 2) { 1184 return OSC_HZ / (div + 1); 1185 } else { 1186 return GPLL_RATE / (div + 1); 1187 } 1188 } 1189 1190 static int clk_scmi_cclk_sdmmc_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1191 { 1192 int div; 1193 1194 if ((OSC_HZ % rate) == 0) { 1195 div = DIV_ROUND_UP(OSC_HZ, rate); 1196 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), 1197 CLKDIV_6BITS_SHF(div - 1, 6) | 1198 BITS_WITH_WMASK(2U, 0x3U, 12)); 1199 } else if ((SPLL_RATE % rate) == 0) { 1200 div = DIV_ROUND_UP(SPLL_RATE, rate); 1201 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), 1202 CLKDIV_6BITS_SHF(div - 1, 6) | 1203 BITS_WITH_WMASK(1U, 0x3U, 12)); 1204 } else { 1205 div = DIV_ROUND_UP(GPLL_RATE, rate); 1206 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), 1207 CLKDIV_6BITS_SHF(div - 1, 6) | 1208 BITS_WITH_WMASK(0U, 0x3U, 12)); 1209 } 1210 1211 return 0; 1212 } 1213 1214 static int clk_scmi_cclk_sdmmc_set_status(rk_scmi_clock_t *clock, bool status) 1215 { 1216 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), 1217 BITS_WITH_WMASK(!status, 0x1U, 4)); 1218 return 0; 1219 } 1220 1221 static unsigned long clk_scmi_dclk_sdmmc_get_rate(rk_scmi_clock_t *clock) 1222 { 1223 int div; 1224 uint32_t src; 1225 1226 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x0020; 1227 div = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x001f; 1228 if (src != 0) { 1229 return SPLL_RATE / (div + 1); 1230 } else { 1231 return GPLL_RATE / (div + 1); 1232 } 1233 } 1234 1235 static int clk_scmi_dclk_sdmmc_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1236 { 1237 int div; 1238 1239 if ((SPLL_RATE % rate) == 0) { 1240 div = DIV_ROUND_UP(SPLL_RATE, rate); 1241 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), 1242 CLKDIV_5BITS_SHF(div - 1, 0) | 1243 BITS_WITH_WMASK(1U, 0x1U, 5)); 1244 } else { 1245 div = DIV_ROUND_UP(GPLL_RATE, rate); 1246 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), 1247 CLKDIV_5BITS_SHF(div - 1, 0) | 1248 BITS_WITH_WMASK(0U, 0x1U, 5)); 1249 } 1250 return 0; 1251 } 1252 1253 static int clk_scmi_dclk_sdmmc_set_status(rk_scmi_clock_t *clock, bool status) 1254 { 1255 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), 1256 BITS_WITH_WMASK(!status, 0x1U, 1)); 1257 return 0; 1258 } 1259 1260 static unsigned long clk_scmi_aclk_secure_ns_get_rate(rk_scmi_clock_t *clock) 1261 { 1262 uint32_t src; 1263 1264 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0003; 1265 switch (src) { 1266 case 0: 1267 return 350 * MHz; 1268 case 1: 1269 return 200 * MHz; 1270 case 2: 1271 return 100 * MHz; 1272 case 3: 1273 return OSC_HZ; 1274 default: 1275 return 0; 1276 } 1277 } 1278 1279 static int clk_scmi_aclk_secure_ns_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1280 { 1281 uint32_t src; 1282 1283 if (rate >= 350 * MHz) 1284 src = 0; 1285 else if (rate >= 200 * MHz) 1286 src = 1; 1287 else if (rate >= 100 * MHz) 1288 src = 2; 1289 else 1290 src = 3; 1291 1292 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), 1293 BITS_WITH_WMASK(src, 0x3U, 0)); 1294 1295 return 0; 1296 } 1297 1298 static int clk_scmi_aclk_secure_ns_set_status(rk_scmi_clock_t *clock, bool status) 1299 { 1300 return 0; 1301 } 1302 1303 static unsigned long clk_scmi_hclk_secure_ns_get_rate(rk_scmi_clock_t *clock) 1304 { 1305 uint32_t src; 1306 1307 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x000c; 1308 src = src >> 2; 1309 switch (src) { 1310 case 0: 1311 return 150 * MHz; 1312 case 1: 1313 return 100 * MHz; 1314 case 2: 1315 return 50 * MHz; 1316 case 3: 1317 return OSC_HZ; 1318 default: 1319 return 0; 1320 } 1321 } 1322 1323 static int clk_scmi_hclk_secure_ns_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1324 { 1325 uint32_t src; 1326 1327 if (rate >= 150 * MHz) 1328 src = 0; 1329 else if (rate >= 100 * MHz) 1330 src = 1; 1331 else if (rate >= 50 * MHz) 1332 src = 2; 1333 else 1334 src = 3; 1335 1336 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), 1337 BITS_WITH_WMASK(src, 0x3U, 2)); 1338 return 0; 1339 } 1340 1341 static int clk_scmi_hclk_secure_ns_set_status(rk_scmi_clock_t *clock, bool status) 1342 { 1343 return 0; 1344 } 1345 1346 static unsigned long clk_scmi_tclk_wdt_get_rate(rk_scmi_clock_t *clock) 1347 { 1348 return OSC_HZ; 1349 } 1350 1351 static int clk_scmi_tclk_wdt_set_status(rk_scmi_clock_t *clock, bool status) 1352 { 1353 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), 1354 BITS_WITH_WMASK(!status, 0x1U, 0)); 1355 return 0; 1356 } 1357 1358 static unsigned long clk_scmi_keyladder_core_get_rate(rk_scmi_clock_t *clock) 1359 { 1360 uint32_t src; 1361 1362 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x00c0; 1363 src = src >> 6; 1364 switch (src) { 1365 case 0: 1366 return 350 * MHz; 1367 case 1: 1368 return 233 * MHz; 1369 case 2: 1370 return 116 * MHz; 1371 case 3: 1372 return OSC_HZ; 1373 default: 1374 return 0; 1375 } 1376 } 1377 1378 static int clk_scmi_keyladder_core_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1379 { 1380 uint32_t src; 1381 1382 if (rate >= 350 * MHz) 1383 src = 0; 1384 else if (rate >= 233 * MHz) 1385 src = 1; 1386 else if (rate >= 116 * MHz) 1387 src = 2; 1388 else 1389 src = 3; 1390 1391 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), 1392 BITS_WITH_WMASK(src, 0x3U, 6)); 1393 return 0; 1394 } 1395 1396 static int clk_scmi_keyladder_core_set_status(rk_scmi_clock_t *clock, bool status) 1397 { 1398 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1399 BITS_WITH_WMASK(!status, 0x1U, 9)); 1400 return 0; 1401 } 1402 1403 static unsigned long clk_scmi_keyladder_rng_get_rate(rk_scmi_clock_t *clock) 1404 { 1405 uint32_t src; 1406 1407 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x0300; 1408 src = src >> 8; 1409 switch (src) { 1410 case 0: 1411 return 175 * MHz; 1412 case 1: 1413 return 116 * MHz; 1414 case 2: 1415 return 58 * MHz; 1416 case 3: 1417 return OSC_HZ; 1418 default: 1419 return 0; 1420 } 1421 } 1422 1423 static int clk_scmi_keyladder_rng_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1424 { 1425 uint32_t src; 1426 1427 if (rate >= 175 * MHz) 1428 src = 0; 1429 else if (rate >= 116 * MHz) 1430 src = 1; 1431 else if (rate >= 58 * MHz) 1432 src = 2; 1433 else 1434 src = 3; 1435 1436 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), 1437 BITS_WITH_WMASK(src, 0x3U, 8)); 1438 return 0; 1439 } 1440 1441 static int clk_scmi_keyladder_rng_set_status(rk_scmi_clock_t *clock, bool status) 1442 { 1443 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1444 BITS_WITH_WMASK(!status, 0x1U, 10)); 1445 return 0; 1446 } 1447 1448 static unsigned long clk_scmi_aclk_secure_s_get_rate(rk_scmi_clock_t *clock) 1449 { 1450 uint32_t src; 1451 1452 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0030; 1453 src = src >> 4; 1454 switch (src) { 1455 case 0: 1456 return 350 * MHz; 1457 case 1: 1458 return 233 * MHz; 1459 case 2: 1460 return 116 * MHz; 1461 case 3: 1462 return OSC_HZ; 1463 default: 1464 return 0; 1465 } 1466 } 1467 1468 static int clk_scmi_aclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1469 { 1470 uint32_t src; 1471 1472 if (rate >= 350 * MHz) 1473 src = 0; 1474 else if (rate >= 233 * MHz) 1475 src = 1; 1476 else if (rate >= 116 * MHz) 1477 src = 2; 1478 else 1479 src = 3; 1480 1481 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), 1482 BITS_WITH_WMASK(src, 0x3U, 4)); 1483 return 0; 1484 } 1485 1486 static int clk_scmi_aclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status) 1487 { 1488 return 0; 1489 } 1490 1491 static unsigned long clk_scmi_hclk_secure_s_get_rate(rk_scmi_clock_t *clock) 1492 { 1493 uint32_t src; 1494 1495 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x00c0; 1496 src = src >> 6; 1497 switch (src) { 1498 case 0: 1499 return 175 * MHz; 1500 case 1: 1501 return 116 * MHz; 1502 case 2: 1503 return 58 * MHz; 1504 case 3: 1505 return OSC_HZ; 1506 default: 1507 return 0; 1508 } 1509 } 1510 1511 static int clk_scmi_hclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1512 { 1513 uint32_t src; 1514 1515 if (rate >= 175 * MHz) 1516 src = 0; 1517 else if (rate >= 116 * MHz) 1518 src = 1; 1519 else if (rate >= 58 * MHz) 1520 src = 2; 1521 else 1522 src = 3; 1523 1524 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), 1525 BITS_WITH_WMASK(src, 0x3U, 6)); 1526 return 0; 1527 } 1528 1529 static int clk_scmi_hclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status) 1530 { 1531 return 0; 1532 } 1533 1534 static unsigned long clk_scmi_pclk_secure_s_get_rate(rk_scmi_clock_t *clock) 1535 { 1536 uint32_t src; 1537 1538 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0300; 1539 src = src >> 8; 1540 switch (src) { 1541 case 0: 1542 return 116 * MHz; 1543 case 1: 1544 return 58 * MHz; 1545 case 2: 1546 return OSC_HZ; 1547 default: 1548 return 0; 1549 } 1550 } 1551 1552 static int clk_scmi_pclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1553 { 1554 uint32_t src; 1555 1556 if (rate >= 116 * MHz) 1557 src = 0; 1558 else if (rate >= 58 * MHz) 1559 src = 1; 1560 else 1561 src = 2; 1562 1563 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), 1564 BITS_WITH_WMASK(src, 0x3U, 8)); 1565 return 0; 1566 } 1567 1568 static int clk_scmi_pclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status) 1569 { 1570 return 0; 1571 } 1572 1573 static unsigned long clk_scmi_crypto_rng_get_rate(rk_scmi_clock_t *clock) 1574 { 1575 uint32_t src; 1576 1577 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0xc000; 1578 src = src >> 14; 1579 switch (src) { 1580 case 0: 1581 return 175 * MHz; 1582 case 1: 1583 return 116 * MHz; 1584 case 2: 1585 return 58 * MHz; 1586 case 3: 1587 return OSC_HZ; 1588 default: 1589 return 0; 1590 } 1591 } 1592 1593 static int clk_scmi_crypto_rng_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1594 { 1595 uint32_t src; 1596 1597 if (rate >= 175 * MHz) 1598 src = 0; 1599 else if (rate >= 116 * MHz) 1600 src = 1; 1601 else if (rate >= 58 * MHz) 1602 src = 2; 1603 else 1604 src = 3; 1605 1606 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), 1607 BITS_WITH_WMASK(src, 0x3U, 14)); 1608 return 0; 1609 } 1610 1611 static int clk_scmi_crypto_rng_set_status(rk_scmi_clock_t *clock, bool status) 1612 { 1613 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1614 BITS_WITH_WMASK(!status, 0x1U, 1)); 1615 1616 return 0; 1617 } 1618 1619 static unsigned long clk_scmi_crypto_core_get_rate(rk_scmi_clock_t *clock) 1620 { 1621 uint32_t src; 1622 1623 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0c00; 1624 src = src >> 10; 1625 switch (src) { 1626 case 0: 1627 return 350 * MHz; 1628 case 1: 1629 return 233 * MHz; 1630 case 2: 1631 return 116 * MHz; 1632 case 3: 1633 return OSC_HZ; 1634 default: 1635 return 0; 1636 } 1637 } 1638 1639 static int clk_scmi_crypto_core_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1640 { 1641 uint32_t src; 1642 1643 if (rate >= 350 * MHz) 1644 src = 0; 1645 else if (rate >= 233 * MHz) 1646 src = 1; 1647 else if (rate >= 116 * MHz) 1648 src = 2; 1649 else 1650 src = 3; 1651 1652 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), 1653 BITS_WITH_WMASK(src, 0x3U, 10)); 1654 return 0; 1655 } 1656 1657 static int clk_scmi_crypto_core_set_status(rk_scmi_clock_t *clock, bool status) 1658 { 1659 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(0), 1660 BITS_WITH_WMASK(!status, 0x1U, 15)); 1661 1662 return 0; 1663 } 1664 1665 static unsigned long clk_scmi_crypto_pka_get_rate(rk_scmi_clock_t *clock) 1666 { 1667 uint32_t src; 1668 1669 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x3000; 1670 src = src >> 12; 1671 switch (src) { 1672 case 0: 1673 return 350 * MHz; 1674 case 1: 1675 return 233 * MHz; 1676 case 2: 1677 return 116 * MHz; 1678 case 3: 1679 return OSC_HZ; 1680 default: 1681 return 0; 1682 } 1683 } 1684 1685 static int clk_scmi_crypto_pka_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1686 { 1687 uint32_t src; 1688 1689 if (rate >= 350 * MHz) 1690 src = 0; 1691 else if (rate >= 233 * MHz) 1692 src = 1; 1693 else if (rate >= 116 * MHz) 1694 src = 2; 1695 else 1696 src = 3; 1697 1698 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1), 1699 BITS_WITH_WMASK(src, 0x3U, 12)); 1700 return 0; 1701 } 1702 1703 static int clk_scmi_crypto_pka_set_status(rk_scmi_clock_t *clock, bool status) 1704 { 1705 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1706 BITS_WITH_WMASK(!status, 0x1U, 0)); 1707 1708 return 0; 1709 } 1710 1711 static unsigned long clk_scmi_spll_get_rate(rk_scmi_clock_t *clock) 1712 { 1713 uint32_t src; 1714 1715 src = mmio_read_32(BUSSCRU_BASE + CRU_MODE_CON0) & 0x3; 1716 switch (src) { 1717 case 0: 1718 return OSC_HZ; 1719 case 1: 1720 return 702 * MHz; 1721 case 2: 1722 return 32768; 1723 default: 1724 return 0; 1725 } 1726 } 1727 1728 static int clk_scmi_spll_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1729 { 1730 uint32_t src; 1731 1732 if (rate >= 700 * MHz) 1733 src = 1; 1734 else 1735 src = 0; 1736 1737 mmio_write_32(BUSSCRU_BASE + CRU_MODE_CON0, 1738 BITS_WITH_WMASK(0, 0x3U, 0)); 1739 mmio_write_32(BUSSCRU_BASE + CRU_PLL_CON(137), 1740 BITS_WITH_WMASK(2, 0x7U, 6)); 1741 1742 mmio_write_32(BUSSCRU_BASE + CRU_MODE_CON0, 1743 BITS_WITH_WMASK(src, 0x3U, 0)); 1744 return 0; 1745 } 1746 1747 static int clk_scmi_spll_set_status(rk_scmi_clock_t *clock, bool status) 1748 { 1749 return 0; 1750 } 1751 1752 static unsigned long clk_scmi_hclk_sd_get_rate(rk_scmi_clock_t *clock) 1753 { 1754 return clk_scmi_hclk_secure_ns_get_rate(clock); 1755 } 1756 1757 static int clk_scmi_hclk_sd_set_status(rk_scmi_clock_t *clock, bool status) 1758 { 1759 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), 1760 BITS_WITH_WMASK(!status, 0x1U, 2)); 1761 return 0; 1762 } 1763 1764 static unsigned long clk_scmi_crypto_rng_s_get_rate(rk_scmi_clock_t *clock) 1765 { 1766 uint32_t src; 1767 1768 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x0030; 1769 src = src >> 4; 1770 switch (src) { 1771 case 0: 1772 return 175 * MHz; 1773 case 1: 1774 return 116 * MHz; 1775 case 2: 1776 return 58 * MHz; 1777 case 3: 1778 return OSC_HZ; 1779 default: 1780 return 0; 1781 } 1782 } 1783 1784 static int clk_scmi_crypto_rng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1785 { 1786 uint32_t src; 1787 1788 if (rate >= 175 * MHz) 1789 src = 0; 1790 else if (rate >= 116 * MHz) 1791 src = 1; 1792 else if (rate >= 58 * MHz) 1793 src = 2; 1794 else 1795 src = 3; 1796 1797 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), 1798 BITS_WITH_WMASK(src, 0x3U, 4)); 1799 return 0; 1800 } 1801 1802 static int clk_scmi_crypto_rng_s_set_status(rk_scmi_clock_t *clock, bool status) 1803 { 1804 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1805 BITS_WITH_WMASK(!status, 0x1U, 6)); 1806 1807 return 0; 1808 } 1809 1810 static unsigned long clk_scmi_crypto_core_s_get_rate(rk_scmi_clock_t *clock) 1811 { 1812 uint32_t src; 1813 1814 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x3; 1815 src = src >> 0; 1816 switch (src) { 1817 case 0: 1818 return 350 * MHz; 1819 case 1: 1820 return 233 * MHz; 1821 case 2: 1822 return 116 * MHz; 1823 case 3: 1824 return OSC_HZ; 1825 default: 1826 return 0; 1827 } 1828 } 1829 1830 static int clk_scmi_crypto_core_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1831 { 1832 uint32_t src; 1833 1834 if (rate >= 350 * MHz) 1835 src = 0; 1836 else if (rate >= 233 * MHz) 1837 src = 1; 1838 else if (rate >= 116 * MHz) 1839 src = 2; 1840 else 1841 src = 3; 1842 1843 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), 1844 BITS_WITH_WMASK(src, 0x3U, 0)); 1845 return 0; 1846 } 1847 1848 static int clk_scmi_crypto_core_s_set_status(rk_scmi_clock_t *clock, bool status) 1849 { 1850 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1851 BITS_WITH_WMASK(!status, 0x1U, 4)); 1852 1853 return 0; 1854 } 1855 1856 static unsigned long clk_scmi_crypto_pka_s_get_rate(rk_scmi_clock_t *clock) 1857 { 1858 uint32_t src; 1859 1860 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x000c; 1861 src = src >> 2; 1862 switch (src) { 1863 case 0: 1864 return 350 * MHz; 1865 case 1: 1866 return 233 * MHz; 1867 case 2: 1868 return 116 * MHz; 1869 case 3: 1870 return OSC_HZ; 1871 default: 1872 return 0; 1873 } 1874 } 1875 1876 static int clk_scmi_crypto_pka_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1877 { 1878 uint32_t src; 1879 1880 if (rate >= 350 * MHz) 1881 src = 0; 1882 else if (rate >= 233 * MHz) 1883 src = 1; 1884 else if (rate >= 116 * MHz) 1885 src = 2; 1886 else 1887 src = 3; 1888 1889 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2), 1890 BITS_WITH_WMASK(src, 0x3U, 2)); 1891 return 0; 1892 } 1893 1894 static int clk_scmi_crypto_pka_s_set_status(rk_scmi_clock_t *clock, bool status) 1895 { 1896 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1897 BITS_WITH_WMASK(!status, 0x1U, 5)); 1898 1899 return 0; 1900 } 1901 1902 static unsigned long clk_scmi_a_crypto_s_get_rate(rk_scmi_clock_t *clock) 1903 { 1904 return clk_scmi_aclk_secure_s_get_rate(clock); 1905 } 1906 1907 static int clk_scmi_a_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1908 { 1909 return clk_scmi_aclk_secure_s_set_rate(clock, rate); 1910 } 1911 1912 static int clk_scmi_a_crypto_s_set_status(rk_scmi_clock_t *clock, bool status) 1913 { 1914 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1915 BITS_WITH_WMASK(!status, 0x1U, 7)); 1916 1917 return 0; 1918 } 1919 1920 static unsigned long clk_scmi_h_crypto_s_get_rate(rk_scmi_clock_t *clock) 1921 { 1922 return clk_scmi_hclk_secure_s_get_rate(clock); 1923 } 1924 1925 static int clk_scmi_h_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1926 { 1927 return clk_scmi_hclk_secure_s_set_rate(clock, rate); 1928 } 1929 1930 static int clk_scmi_h_crypto_s_set_status(rk_scmi_clock_t *clock, bool status) 1931 { 1932 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1933 BITS_WITH_WMASK(!status, 0x1U, 8)); 1934 1935 return 0; 1936 } 1937 1938 static unsigned long clk_scmi_p_crypto_s_get_rate(rk_scmi_clock_t *clock) 1939 { 1940 return clk_scmi_pclk_secure_s_get_rate(clock); 1941 } 1942 1943 static int clk_scmi_p_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1944 { 1945 return clk_scmi_pclk_secure_s_set_rate(clock, rate); 1946 } 1947 1948 static int clk_scmi_p_crypto_s_set_status(rk_scmi_clock_t *clock, bool status) 1949 { 1950 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), 1951 BITS_WITH_WMASK(!status, 0x1U, 13)); 1952 1953 return 0; 1954 } 1955 1956 static unsigned long clk_scmi_a_keylad_s_get_rate(rk_scmi_clock_t *clock) 1957 { 1958 return clk_scmi_aclk_secure_s_get_rate(clock); 1959 } 1960 1961 static int clk_scmi_a_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1962 { 1963 return clk_scmi_aclk_secure_s_set_rate(clock, rate); 1964 } 1965 1966 static int clk_scmi_a_keylad_s_set_status(rk_scmi_clock_t *clock, bool status) 1967 { 1968 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1969 BITS_WITH_WMASK(!status, 0x1U, 11)); 1970 1971 return 0; 1972 } 1973 1974 static unsigned long clk_scmi_h_keylad_s_get_rate(rk_scmi_clock_t *clock) 1975 { 1976 return clk_scmi_hclk_secure_s_get_rate(clock); 1977 } 1978 1979 static int clk_scmi_h_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1980 { 1981 return clk_scmi_hclk_secure_s_set_rate(clock, rate); 1982 } 1983 1984 static int clk_scmi_h_keylad_s_set_status(rk_scmi_clock_t *clock, bool status) 1985 { 1986 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 1987 BITS_WITH_WMASK(!status, 0x1U, 12)); 1988 1989 return 0; 1990 } 1991 1992 static unsigned long clk_scmi_p_keylad_s_get_rate(rk_scmi_clock_t *clock) 1993 { 1994 return clk_scmi_pclk_secure_s_get_rate(clock); 1995 } 1996 1997 static int clk_scmi_p_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 1998 { 1999 return clk_scmi_pclk_secure_s_set_rate(clock, rate); 2000 } 2001 2002 static int clk_scmi_p_keylad_s_set_status(rk_scmi_clock_t *clock, bool status) 2003 { 2004 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), 2005 BITS_WITH_WMASK(!status, 0x1U, 14)); 2006 2007 return 0; 2008 } 2009 2010 static unsigned long clk_scmi_trng_s_get_rate(rk_scmi_clock_t *clock) 2011 { 2012 return clk_scmi_hclk_secure_s_get_rate(clock); 2013 } 2014 2015 static int clk_scmi_trng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 2016 { 2017 return clk_scmi_hclk_secure_s_set_rate(clock, rate); 2018 } 2019 2020 static int clk_scmi_trng_s_set_status(rk_scmi_clock_t *clock, bool status) 2021 { 2022 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), 2023 BITS_WITH_WMASK(!status, 0x1U, 6)); 2024 2025 return 0; 2026 } 2027 2028 static unsigned long clk_scmi_h_trng_s_get_rate(rk_scmi_clock_t *clock) 2029 { 2030 return clk_scmi_hclk_secure_s_get_rate(clock); 2031 } 2032 2033 static int clk_scmi_h_trng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 2034 { 2035 return clk_scmi_hclk_secure_s_set_rate(clock, rate); 2036 } 2037 2038 static int clk_scmi_h_trng_s_set_status(rk_scmi_clock_t *clock, bool status) 2039 { 2040 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), 2041 BITS_WITH_WMASK(!status, 0x1U, 15)); 2042 2043 return 0; 2044 } 2045 2046 static unsigned long clk_scmi_p_otpc_s_get_rate(rk_scmi_clock_t *clock) 2047 { 2048 return clk_scmi_pclk_secure_s_get_rate(clock); 2049 } 2050 2051 static int clk_scmi_p_otpc_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate) 2052 { 2053 return clk_scmi_pclk_secure_s_set_rate(clock, rate); 2054 } 2055 2056 static int clk_scmi_p_otpc_s_set_status(rk_scmi_clock_t *clock, bool status) 2057 { 2058 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 2059 BITS_WITH_WMASK(!status, 0x1U, 13)); 2060 2061 return 0; 2062 } 2063 2064 static unsigned long clk_scmi_otpc_s_get_rate(rk_scmi_clock_t *clock) 2065 { 2066 return OSC_HZ; 2067 } 2068 2069 static int clk_scmi_otpc_s_set_status(rk_scmi_clock_t *clock, bool status) 2070 { 2071 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), 2072 BITS_WITH_WMASK(!status, 0x1U, 14)); 2073 return 0; 2074 } 2075 2076 static unsigned long clk_scmi_otp_phy_get_rate(rk_scmi_clock_t *clock) 2077 { 2078 return OSC_HZ; 2079 } 2080 2081 static int clk_scmi_otp_phy_set_status(rk_scmi_clock_t *clock, bool status) 2082 { 2083 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), 2084 BITS_WITH_WMASK(!status, 0x1U, 13)); 2085 return 0; 2086 } 2087 2088 static unsigned long clk_scmi_otpc_rd_get_rate(rk_scmi_clock_t *clock) 2089 { 2090 return OSC_HZ; 2091 } 2092 2093 static int clk_scmi_otpc_rd_set_status(rk_scmi_clock_t *clock, bool status) 2094 { 2095 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), 2096 BITS_WITH_WMASK(!status, 0x1U, 12)); 2097 return 0; 2098 } 2099 2100 static unsigned long clk_scmi_otpc_arb_get_rate(rk_scmi_clock_t *clock) 2101 { 2102 return OSC_HZ; 2103 } 2104 2105 static int clk_scmi_otpc_arb_set_status(rk_scmi_clock_t *clock, bool status) 2106 { 2107 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), 2108 BITS_WITH_WMASK(!status, 0x1U, 11)); 2109 return 0; 2110 } 2111 2112 static const struct rk_clk_ops clk_scmi_cpul_ops = { 2113 .get_rate = clk_scmi_cpul_get_rate, 2114 .set_rate = clk_scmi_cpul_set_rate, 2115 .set_status = clk_scmi_cpul_set_status, 2116 }; 2117 2118 static const struct rk_clk_ops clk_scmi_dsu_ops = { 2119 .get_rate = clk_scmi_dsu_get_rate, 2120 .set_rate = clk_scmi_dsu_set_rate, 2121 .set_status = clk_scmi_dsu_set_status, 2122 }; 2123 2124 static const struct rk_clk_ops clk_scmi_cpub01_ops = { 2125 .get_rate = clk_scmi_cpub01_get_rate, 2126 .set_rate = clk_scmi_cpub01_set_rate, 2127 .set_status = clk_scmi_cpub01_set_status, 2128 }; 2129 2130 static const struct rk_clk_ops clk_scmi_cpub23_ops = { 2131 .get_rate = clk_scmi_cpub23_get_rate, 2132 .set_rate = clk_scmi_cpub23_set_rate, 2133 .set_status = clk_scmi_cpub23_set_status, 2134 }; 2135 2136 static const struct rk_clk_ops clk_scmi_gpu_ops = { 2137 .get_rate = clk_scmi_gpu_get_rate, 2138 .set_rate = clk_scmi_gpu_set_rate, 2139 .set_status = clk_scmi_gpu_set_status, 2140 }; 2141 2142 static const struct rk_clk_ops clk_scmi_npu_ops = { 2143 .get_rate = clk_scmi_npu_get_rate, 2144 .set_rate = clk_scmi_npu_set_rate, 2145 .set_status = clk_scmi_npu_set_status, 2146 }; 2147 2148 static const struct rk_clk_ops clk_scmi_sbus_ops = { 2149 .get_rate = clk_scmi_sbus_get_rate, 2150 .set_rate = clk_scmi_sbus_set_rate, 2151 .set_status = clk_scmi_sbus_set_status, 2152 }; 2153 2154 static const struct rk_clk_ops clk_scmi_pclk_sbus_ops = { 2155 .get_rate = clk_scmi_pclk_sbus_get_rate, 2156 .set_rate = clk_scmi_pclk_sbus_set_rate, 2157 .set_status = clk_scmi_pclk_sbus_set_status, 2158 }; 2159 2160 static const struct rk_clk_ops clk_scmi_cclk_sdmmc_ops = { 2161 .get_rate = clk_scmi_cclk_sdmmc_get_rate, 2162 .set_rate = clk_scmi_cclk_sdmmc_set_rate, 2163 .set_status = clk_scmi_cclk_sdmmc_set_status, 2164 }; 2165 2166 static const struct rk_clk_ops clk_scmi_dclk_sdmmc_ops = { 2167 .get_rate = clk_scmi_dclk_sdmmc_get_rate, 2168 .set_rate = clk_scmi_dclk_sdmmc_set_rate, 2169 .set_status = clk_scmi_dclk_sdmmc_set_status, 2170 }; 2171 2172 static const struct rk_clk_ops clk_scmi_aclk_secure_ns_ops = { 2173 .get_rate = clk_scmi_aclk_secure_ns_get_rate, 2174 .set_rate = clk_scmi_aclk_secure_ns_set_rate, 2175 .set_status = clk_scmi_aclk_secure_ns_set_status, 2176 }; 2177 2178 static const struct rk_clk_ops clk_scmi_hclk_secure_ns_ops = { 2179 .get_rate = clk_scmi_hclk_secure_ns_get_rate, 2180 .set_rate = clk_scmi_hclk_secure_ns_set_rate, 2181 .set_status = clk_scmi_hclk_secure_ns_set_status, 2182 }; 2183 2184 static const struct rk_clk_ops clk_scmi_tclk_wdt_ops = { 2185 .get_rate = clk_scmi_tclk_wdt_get_rate, 2186 .set_status = clk_scmi_tclk_wdt_set_status, 2187 }; 2188 2189 static const struct rk_clk_ops clk_scmi_keyladder_core_ops = { 2190 .get_rate = clk_scmi_keyladder_core_get_rate, 2191 .set_rate = clk_scmi_keyladder_core_set_rate, 2192 .set_status = clk_scmi_keyladder_core_set_status, 2193 }; 2194 2195 static const struct rk_clk_ops clk_scmi_keyladder_rng_ops = { 2196 .get_rate = clk_scmi_keyladder_rng_get_rate, 2197 .set_rate = clk_scmi_keyladder_rng_set_rate, 2198 .set_status = clk_scmi_keyladder_rng_set_status, 2199 }; 2200 2201 static const struct rk_clk_ops clk_scmi_aclk_secure_s_ops = { 2202 .get_rate = clk_scmi_aclk_secure_s_get_rate, 2203 .set_rate = clk_scmi_aclk_secure_s_set_rate, 2204 .set_status = clk_scmi_aclk_secure_s_set_status, 2205 }; 2206 2207 static const struct rk_clk_ops clk_scmi_hclk_secure_s_ops = { 2208 .get_rate = clk_scmi_hclk_secure_s_get_rate, 2209 .set_rate = clk_scmi_hclk_secure_s_set_rate, 2210 .set_status = clk_scmi_hclk_secure_s_set_status, 2211 }; 2212 2213 static const struct rk_clk_ops clk_scmi_pclk_secure_s_ops = { 2214 .get_rate = clk_scmi_pclk_secure_s_get_rate, 2215 .set_rate = clk_scmi_pclk_secure_s_set_rate, 2216 .set_status = clk_scmi_pclk_secure_s_set_status, 2217 }; 2218 2219 static const struct rk_clk_ops clk_scmi_crypto_rng_ops = { 2220 .get_rate = clk_scmi_crypto_rng_get_rate, 2221 .set_rate = clk_scmi_crypto_rng_set_rate, 2222 .set_status = clk_scmi_crypto_rng_set_status, 2223 }; 2224 2225 static const struct rk_clk_ops clk_scmi_crypto_core_ops = { 2226 .get_rate = clk_scmi_crypto_core_get_rate, 2227 .set_rate = clk_scmi_crypto_core_set_rate, 2228 .set_status = clk_scmi_crypto_core_set_status, 2229 }; 2230 2231 static const struct rk_clk_ops clk_scmi_crypto_pka_ops = { 2232 .get_rate = clk_scmi_crypto_pka_get_rate, 2233 .set_rate = clk_scmi_crypto_pka_set_rate, 2234 .set_status = clk_scmi_crypto_pka_set_status, 2235 }; 2236 2237 static const struct rk_clk_ops clk_scmi_spll_ops = { 2238 .get_rate = clk_scmi_spll_get_rate, 2239 .set_rate = clk_scmi_spll_set_rate, 2240 .set_status = clk_scmi_spll_set_status, 2241 }; 2242 2243 static const struct rk_clk_ops clk_scmi_hclk_sd_ops = { 2244 .get_rate = clk_scmi_hclk_sd_get_rate, 2245 .set_status = clk_scmi_hclk_sd_set_status, 2246 }; 2247 2248 static const struct rk_clk_ops clk_scmi_crypto_rng_s_ops = { 2249 .get_rate = clk_scmi_crypto_rng_s_get_rate, 2250 .set_rate = clk_scmi_crypto_rng_s_set_rate, 2251 .set_status = clk_scmi_crypto_rng_s_set_status, 2252 }; 2253 2254 static const struct rk_clk_ops clk_scmi_crypto_core_s_ops = { 2255 .get_rate = clk_scmi_crypto_core_s_get_rate, 2256 .set_rate = clk_scmi_crypto_core_s_set_rate, 2257 .set_status = clk_scmi_crypto_core_s_set_status, 2258 }; 2259 2260 static const struct rk_clk_ops clk_scmi_crypto_pka_s_ops = { 2261 .get_rate = clk_scmi_crypto_pka_s_get_rate, 2262 .set_rate = clk_scmi_crypto_pka_s_set_rate, 2263 .set_status = clk_scmi_crypto_pka_s_set_status, 2264 }; 2265 2266 static const struct rk_clk_ops clk_scmi_a_crypto_s_ops = { 2267 .get_rate = clk_scmi_a_crypto_s_get_rate, 2268 .set_rate = clk_scmi_a_crypto_s_set_rate, 2269 .set_status = clk_scmi_a_crypto_s_set_status, 2270 }; 2271 2272 static const struct rk_clk_ops clk_scmi_h_crypto_s_ops = { 2273 .get_rate = clk_scmi_h_crypto_s_get_rate, 2274 .set_rate = clk_scmi_h_crypto_s_set_rate, 2275 .set_status = clk_scmi_h_crypto_s_set_status, 2276 }; 2277 2278 static const struct rk_clk_ops clk_scmi_p_crypto_s_ops = { 2279 .get_rate = clk_scmi_p_crypto_s_get_rate, 2280 .set_rate = clk_scmi_p_crypto_s_set_rate, 2281 .set_status = clk_scmi_p_crypto_s_set_status, 2282 }; 2283 2284 static const struct rk_clk_ops clk_scmi_a_keylad_s_ops = { 2285 .get_rate = clk_scmi_a_keylad_s_get_rate, 2286 .set_rate = clk_scmi_a_keylad_s_set_rate, 2287 .set_status = clk_scmi_a_keylad_s_set_status, 2288 }; 2289 2290 static const struct rk_clk_ops clk_scmi_h_keylad_s_ops = { 2291 .get_rate = clk_scmi_h_keylad_s_get_rate, 2292 .set_rate = clk_scmi_h_keylad_s_set_rate, 2293 .set_status = clk_scmi_h_keylad_s_set_status, 2294 }; 2295 2296 static const struct rk_clk_ops clk_scmi_p_keylad_s_ops = { 2297 .get_rate = clk_scmi_p_keylad_s_get_rate, 2298 .set_rate = clk_scmi_p_keylad_s_set_rate, 2299 .set_status = clk_scmi_p_keylad_s_set_status, 2300 }; 2301 2302 static const struct rk_clk_ops clk_scmi_trng_s_ops = { 2303 .get_rate = clk_scmi_trng_s_get_rate, 2304 .set_rate = clk_scmi_trng_s_set_rate, 2305 .set_status = clk_scmi_trng_s_set_status, 2306 }; 2307 2308 static const struct rk_clk_ops clk_scmi_h_trng_s_ops = { 2309 .get_rate = clk_scmi_h_trng_s_get_rate, 2310 .set_rate = clk_scmi_h_trng_s_set_rate, 2311 .set_status = clk_scmi_h_trng_s_set_status, 2312 }; 2313 2314 static const struct rk_clk_ops clk_scmi_p_otpc_s_ops = { 2315 .get_rate = clk_scmi_p_otpc_s_get_rate, 2316 .set_rate = clk_scmi_p_otpc_s_set_rate, 2317 .set_status = clk_scmi_p_otpc_s_set_status, 2318 }; 2319 2320 static const struct rk_clk_ops clk_scmi_otpc_s_ops = { 2321 .get_rate = clk_scmi_otpc_s_get_rate, 2322 .set_status = clk_scmi_otpc_s_set_status, 2323 }; 2324 2325 static const struct rk_clk_ops clk_scmi_otp_phy_ops = { 2326 .get_rate = clk_scmi_otp_phy_get_rate, 2327 .set_status = clk_scmi_otp_phy_set_status, 2328 }; 2329 2330 static const struct rk_clk_ops clk_scmi_otpc_rd_ops = { 2331 .get_rate = clk_scmi_otpc_rd_get_rate, 2332 .set_status = clk_scmi_otpc_rd_set_status, 2333 }; 2334 2335 static const struct rk_clk_ops clk_scmi_otpc_arb_ops = { 2336 .get_rate = clk_scmi_otpc_arb_get_rate, 2337 .set_status = clk_scmi_otpc_arb_set_status, 2338 }; 2339 2340 rk_scmi_clock_t clock_table[] = { 2341 RK3588_SCMI_CLOCK(SCMI_CLK_CPUL, "scmi_clk_cpul", &clk_scmi_cpul_ops, rk3588_cpul_rates, ARRAY_SIZE(rk3588_cpul_rates), false), 2342 RK3588_SCMI_CLOCK(SCMI_CLK_DSU, "scmi_clk_dsu", &clk_scmi_dsu_ops, rk3588_cpul_rates, ARRAY_SIZE(rk3588_cpul_rates), false), 2343 RK3588_SCMI_CLOCK(SCMI_CLK_CPUB01, "scmi_clk_cpub01", &clk_scmi_cpub01_ops, rk3588_cpub_rates, ARRAY_SIZE(rk3588_cpub_rates), false), 2344 RK3588_SCMI_CLOCK(SCMI_CLK_CPUB23, "scmi_clk_cpub23", &clk_scmi_cpub23_ops, rk3588_cpub_rates, ARRAY_SIZE(rk3588_cpub_rates), false), 2345 RK3588_SCMI_CLOCK(SCMI_CLK_DDR, "scmi_clk_ddr", NULL, NULL, 0, false), 2346 RK3588_SCMI_CLOCK(SCMI_CLK_GPU, "scmi_clk_gpu", &clk_scmi_gpu_ops, rk3588_gpu_rates, ARRAY_SIZE(rk3588_gpu_rates), false), 2347 RK3588_SCMI_CLOCK(SCMI_CLK_NPU, "scmi_clk_npu", &clk_scmi_npu_ops, rk3588_gpu_rates, ARRAY_SIZE(rk3588_gpu_rates), false), 2348 RK3588_SCMI_CLOCK(SCMI_CLK_SBUS, "scmi_clk_sbus", &clk_scmi_sbus_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2349 RK3588_SCMI_CLOCK(SCMI_PCLK_SBUS, "scmi_pclk_sbus", &clk_scmi_pclk_sbus_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2350 RK3588_SCMI_CLOCK(SCMI_CCLK_SD, "scmi_cclk_sd", &clk_scmi_cclk_sdmmc_ops, rk3588_sdmmc_rates, ARRAY_SIZE(rk3588_sdmmc_rates), false), 2351 RK3588_SCMI_CLOCK(SCMI_DCLK_SD, "scmi_dclk_sd", &clk_scmi_dclk_sdmmc_ops, rk3588_sdmmc_rates, ARRAY_SIZE(rk3588_sdmmc_rates), false), 2352 RK3588_SCMI_CLOCK(SCMI_ACLK_SECURE_NS, "scmi_aclk_se_ns", &clk_scmi_aclk_secure_ns_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), 2353 RK3588_SCMI_CLOCK(SCMI_HCLK_SECURE_NS, "scmi_hclk_se_ns", &clk_scmi_hclk_secure_ns_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), 2354 RK3588_SCMI_CLOCK(SCMI_TCLK_WDT, "scmi_tclk_wdt", &clk_scmi_tclk_wdt_ops, NULL, 0, false), 2355 RK3588_SCMI_CLOCK(SCMI_KEYLADDER_CORE, "scmi_keylad_c", &clk_scmi_keyladder_core_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2356 RK3588_SCMI_CLOCK(SCMI_KEYLADDER_RNG, "scmi_keylad_r", &clk_scmi_keyladder_rng_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2357 RK3588_SCMI_CLOCK(SCMI_ACLK_SECURE_S, "scmi_aclk_se_s", &clk_scmi_aclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2358 RK3588_SCMI_CLOCK(SCMI_HCLK_SECURE_S, "scmi_hclk_se_s", &clk_scmi_hclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2359 RK3588_SCMI_CLOCK(SCMI_PCLK_SECURE_S, "scmi_pclk_se_s", &clk_scmi_pclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2360 RK3588_SCMI_CLOCK(SCMI_CRYPTO_RNG, "scmi_crypto_r", &clk_scmi_crypto_rng_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), 2361 RK3588_SCMI_CLOCK(SCMI_CRYPTO_CORE, "scmi_crypto_c", &clk_scmi_crypto_core_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), 2362 RK3588_SCMI_CLOCK(SCMI_CRYPTO_PKA, "scmi_crypto_p", &clk_scmi_crypto_pka_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), 2363 RK3588_SCMI_CLOCK(SCMI_SPLL, "scmi_spll", &clk_scmi_spll_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false), 2364 RK3588_SCMI_CLOCK(SCMI_HCLK_SD, "scmi_hclk_sd", &clk_scmi_hclk_sd_ops, NULL, 0, false), 2365 RK3588_SCMI_CLOCK(SCMI_CRYPTO_RNG_S, "scmi_crypto_r_s", &clk_scmi_crypto_rng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2366 RK3588_SCMI_CLOCK(SCMI_CRYPTO_CORE_S, "scmi_crypto_c_s", &clk_scmi_crypto_core_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2367 RK3588_SCMI_CLOCK(SCMI_CRYPTO_PKA_S, "scmi_crypto_p_s", &clk_scmi_crypto_pka_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2368 RK3588_SCMI_CLOCK(SCMI_A_CRYPTO_S, "scmi_a_crypto_s", &clk_scmi_a_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2369 RK3588_SCMI_CLOCK(SCMI_H_CRYPTO_S, "scmi_h_crypto_s", &clk_scmi_h_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2370 RK3588_SCMI_CLOCK(SCMI_P_CRYPTO_S, "scmi_p_crypto_s", &clk_scmi_p_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2371 RK3588_SCMI_CLOCK(SCMI_A_KEYLADDER_S, "scmi_a_keylad_s", &clk_scmi_a_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2372 RK3588_SCMI_CLOCK(SCMI_H_KEYLADDER_S, "scmi_h_keylad_s", &clk_scmi_h_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2373 RK3588_SCMI_CLOCK(SCMI_P_KEYLADDER_S, "scmi_p_keylad_s", &clk_scmi_p_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2374 RK3588_SCMI_CLOCK(SCMI_TRNG_S, "scmi_trng_s", &clk_scmi_trng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2375 RK3588_SCMI_CLOCK(SCMI_H_TRNG_S, "scmi_h_trng_s", &clk_scmi_h_trng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2376 RK3588_SCMI_CLOCK(SCMI_P_OTPC_S, "scmi_p_otpc_s", &clk_scmi_p_otpc_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true), 2377 RK3588_SCMI_CLOCK(SCMI_OTPC_S, "scmi_otpc_s", &clk_scmi_otpc_s_ops, NULL, 0, true), 2378 RK3588_SCMI_CLOCK(SCMI_OTP_PHY, "scmi_otp_phy", &clk_scmi_otp_phy_ops, NULL, 0, false), 2379 RK3588_SCMI_CLOCK(SCMI_OTPC_AUTO_RD, "scmi_otpc_rd", &clk_scmi_otpc_rd_ops, NULL, 0, false), 2380 RK3588_SCMI_CLOCK(SCMI_OTPC_ARB, "scmi_otpc_arb", &clk_scmi_otpc_arb_ops, NULL, 0, false), 2381 }; 2382 2383 size_t rockchip_scmi_clock_count(unsigned int agent_id __unused) 2384 { 2385 return ARRAY_SIZE(clock_table); 2386 } 2387 2388 rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id __unused, 2389 uint32_t clock_id) 2390 { 2391 rk_scmi_clock_t *table = NULL; 2392 2393 if (clock_id < ARRAY_SIZE(clock_table)) 2394 table = &clock_table[clock_id]; 2395 2396 if (table && !table->is_security) 2397 return table; 2398 else 2399 return NULL; 2400 } 2401 2402 void pvtplls_suspend(void) 2403 { 2404 clk_cpul_set_rate(408000000, PLL_SEL_NOR); 2405 clk_dsu_set_rate(408000000, PLL_SEL_NOR); 2406 clk_cpub01_set_rate(408000000, PLL_SEL_NOR); 2407 clk_cpub23_set_rate(408000000, PLL_SEL_NOR); 2408 } 2409 2410 void pvtplls_resume(void) 2411 { 2412 clk_cpul_set_rate(sys_clk_info.cpul_rate, PLL_SEL_AUTO); 2413 clk_dsu_set_rate(sys_clk_info.dsu_rate, PLL_SEL_AUTO); 2414 clk_cpub01_set_rate(sys_clk_info.cpub01_rate, PLL_SEL_AUTO); 2415 clk_cpub23_set_rate(sys_clk_info.cpub23_rate, PLL_SEL_AUTO); 2416 } 2417 2418 void sys_reset_pvtplls_prepare(void) 2419 { 2420 clk_gpu_set_rate(100000000, PLL_SEL_NOR); 2421 clk_npu_set_rate(100000000, PLL_SEL_NOR); 2422 clk_cpul_set_rate(408000000, PLL_SEL_NOR); 2423 clk_cpub01_set_rate(408000000, PLL_SEL_NOR); 2424 clk_cpub23_set_rate(408000000, PLL_SEL_NOR); 2425 clk_dsu_set_rate(408000000, PLL_SEL_NOR); 2426 } 2427 2428 void rockchip_clock_init(void) 2429 { 2430 /* set gpll src div to 0 for cpul */ 2431 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), CLKDIV_5BITS_SHF(0U, 9)); 2432 /* set gpll src div to 0 for cpub01 */ 2433 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0), 2434 CLKDIV_5BITS_SHF(0U, 1)); 2435 /* set gpll src div to 0 for cpu23 */ 2436 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0), 2437 CLKDIV_5BITS_SHF(0U, 1)); 2438 2439 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), 2440 CPUB_PCLK_PATH_50M); 2441 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), 2442 CPUB_PCLK_PATH_50M); 2443 2444 mmio_write_32(DSUCRU_BASE + DSUCRU_CLKSEL_CON(4), 2445 CLKDIV_5BITS_SHF(5U, 0)); 2446 mmio_write_32(DSUCRU_BASE + DSUCRU_CLKSEL_CON(4), 2447 BITS_WITH_WMASK(PCLK_DSU_ROOT_SEL_GPLL, 2448 PCLK_DSU_ROOT_SEL_MASK, 2449 PCLK_DSU_ROOT_SEL_SHIFT)); 2450 2451 sys_clk_info.cpul_table = rk3588_cpul_pvtpll_table; 2452 sys_clk_info.cpul_rate_count = ARRAY_SIZE(rk3588_cpul_pvtpll_table); 2453 sys_clk_info.cpub01_table = rk3588_cpub0_pvtpll_table; 2454 sys_clk_info.cpub01_rate_count = ARRAY_SIZE(rk3588_cpub0_pvtpll_table); 2455 sys_clk_info.cpub23_table = rk3588_cpub1_pvtpll_table; 2456 sys_clk_info.cpub23_rate_count = ARRAY_SIZE(rk3588_cpub1_pvtpll_table); 2457 memcpy(sys_clk_info.cpub23_table, sys_clk_info.cpub01_table, 2458 sys_clk_info.cpub01_rate_count * sizeof(*sys_clk_info.cpub01_table)); 2459 sys_clk_info.gpu_table = rk3588_gpu_pvtpll_table; 2460 sys_clk_info.gpu_rate_count = ARRAY_SIZE(rk3588_gpu_pvtpll_table); 2461 sys_clk_info.npu_table = rk3588_npu_pvtpll_table; 2462 sys_clk_info.npu_rate_count = ARRAY_SIZE(rk3588_npu_pvtpll_table); 2463 } 2464