1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __CLOCK_H__ 7 #define __CLOCK_H__ 8 9 /* cru-clocks indices */ 10 11 /* cru plls */ 12 #define PLL_BPLL 1 13 #define PLL_LPLL 3 14 #define PLL_VPLL 4 15 #define PLL_AUPLL 5 16 #define PLL_CPLL 6 17 #define PLL_GPLL 7 18 #define PLL_PPLL 9 19 #define ARMCLK_L 10 20 #define ARMCLK_B 11 21 22 /* cru clocks */ 23 #define CLK_CPLL_DIV20 15 24 #define CLK_CPLL_DIV10 16 25 #define CLK_GPLL_DIV8 17 26 #define CLK_GPLL_DIV6 18 27 #define CLK_CPLL_DIV4 19 28 #define CLK_GPLL_DIV4 20 29 #define CLK_SPLL_DIV2 21 30 #define CLK_GPLL_DIV3 22 31 #define CLK_CPLL_DIV2 23 32 #define CLK_GPLL_DIV2 24 33 #define CLK_SPLL_DIV1 25 34 #define PCLK_TOP_ROOT 26 35 #define ACLK_TOP 27 36 #define HCLK_TOP 28 37 #define CLK_AUDIO_FRAC_0 29 38 #define CLK_AUDIO_FRAC_1 30 39 #define CLK_AUDIO_FRAC_2 31 40 #define CLK_AUDIO_FRAC_3 32 41 #define CLK_UART_FRAC_0 33 42 #define CLK_UART_FRAC_1 34 43 #define CLK_UART_FRAC_2 35 44 #define CLK_UART1_SRC_TOP 36 45 #define CLK_AUDIO_INT_0 37 46 #define CLK_AUDIO_INT_1 38 47 #define CLK_AUDIO_INT_2 39 48 #define CLK_PDM0_SRC_TOP 40 49 #define CLK_PDM1_OUT 41 50 #define CLK_GMAC0_125M_SRC 42 51 #define CLK_GMAC1_125M_SRC 43 52 #define LCLK_ASRC_SRC_0 44 53 #define LCLK_ASRC_SRC_1 45 54 #define REF_CLK0_OUT_PLL 46 55 #define REF_CLK1_OUT_PLL 47 56 #define REF_CLK2_OUT_PLL 48 57 #define REFCLKO25M_GMAC0_OUT 49 58 #define REFCLKO25M_GMAC1_OUT 50 59 #define CLK_CIFOUT_OUT 51 60 #define CLK_GMAC0_RMII_CRU 52 61 #define CLK_GMAC1_RMII_CRU 53 62 #define CLK_OTPC_AUTO_RD_G 54 63 #define CLK_OTP_PHY_G 55 64 #define CLK_MIPI_CAMERAOUT_M0 56 65 #define CLK_MIPI_CAMERAOUT_M1 57 66 #define CLK_MIPI_CAMERAOUT_M2 58 67 #define MCLK_PDM0_SRC_TOP 59 68 #define HCLK_AUDIO_ROOT 60 69 #define HCLK_ASRC_2CH_0 61 70 #define HCLK_ASRC_2CH_1 62 71 #define HCLK_ASRC_4CH_0 63 72 #define HCLK_ASRC_4CH_1 64 73 #define CLK_ASRC_2CH_0 65 74 #define CLK_ASRC_2CH_1 66 75 #define CLK_ASRC_4CH_0 67 76 #define CLK_ASRC_4CH_1 68 77 #define MCLK_SAI0_8CH_SRC 69 78 #define MCLK_SAI0_8CH 70 79 #define HCLK_SAI0_8CH 71 80 #define HCLK_SPDIF_RX0 72 81 #define MCLK_SPDIF_RX0 73 82 #define HCLK_SPDIF_RX1 74 83 #define MCLK_SPDIF_RX1 75 84 #define MCLK_SAI1_8CH_SRC 76 85 #define MCLK_SAI1_8CH 77 86 #define HCLK_SAI1_8CH 78 87 #define MCLK_SAI2_2CH_SRC 79 88 #define MCLK_SAI2_2CH 80 89 #define HCLK_SAI2_2CH 81 90 #define MCLK_SAI3_2CH_SRC 82 91 #define MCLK_SAI3_2CH 83 92 #define HCLK_SAI3_2CH 84 93 #define MCLK_SAI4_2CH_SRC 85 94 #define MCLK_SAI4_2CH 86 95 #define HCLK_SAI4_2CH 87 96 #define HCLK_ACDCDIG_DSM 88 97 #define MCLK_ACDCDIG_DSM 89 98 #define CLK_PDM1 90 99 #define HCLK_PDM1 91 100 #define MCLK_PDM1 92 101 #define HCLK_SPDIF_TX0 93 102 #define MCLK_SPDIF_TX0 94 103 #define HCLK_SPDIF_TX1 95 104 #define MCLK_SPDIF_TX1 96 105 #define CLK_SAI1_MCLKOUT 97 106 #define CLK_SAI2_MCLKOUT 98 107 #define CLK_SAI3_MCLKOUT 99 108 #define CLK_SAI4_MCLKOUT 100 109 #define CLK_SAI0_MCLKOUT 101 110 #define HCLK_BUS_ROOT 102 111 #define PCLK_BUS_ROOT 103 112 #define ACLK_BUS_ROOT 104 113 #define HCLK_CAN0 105 114 #define CLK_CAN0 106 115 #define HCLK_CAN1 107 116 #define CLK_CAN1 108 117 #define CLK_KEY_SHIFT 109 118 #define PCLK_I2C1 110 119 #define PCLK_I2C2 111 120 #define PCLK_I2C3 112 121 #define PCLK_I2C4 113 122 #define PCLK_I2C5 114 123 #define PCLK_I2C6 115 124 #define PCLK_I2C7 116 125 #define PCLK_I2C8 117 126 #define PCLK_I2C9 118 127 #define PCLK_WDT_BUSMCU 119 128 #define TCLK_WDT_BUSMCU 120 129 #define ACLK_GIC 121 130 #define CLK_I2C1 122 131 #define CLK_I2C2 123 132 #define CLK_I2C3 124 133 #define CLK_I2C4 125 134 #define CLK_I2C5 126 135 #define CLK_I2C6 127 136 #define CLK_I2C7 128 137 #define CLK_I2C8 129 138 #define CLK_I2C9 130 139 #define PCLK_SARADC 131 140 #define CLK_SARADC 132 141 #define PCLK_TSADC 133 142 #define CLK_TSADC 134 143 #define PCLK_UART0 135 144 #define PCLK_UART2 136 145 #define PCLK_UART3 137 146 #define PCLK_UART4 138 147 #define PCLK_UART5 139 148 #define PCLK_UART6 140 149 #define PCLK_UART7 141 150 #define PCLK_UART8 142 151 #define PCLK_UART9 143 152 #define PCLK_UART10 144 153 #define PCLK_UART11 145 154 #define SCLK_UART0 146 155 #define SCLK_UART2 147 156 #define SCLK_UART3 148 157 #define SCLK_UART4 149 158 #define SCLK_UART5 150 159 #define SCLK_UART6 151 160 #define SCLK_UART7 152 161 #define SCLK_UART8 153 162 #define SCLK_UART9 154 163 #define SCLK_UART10 155 164 #define SCLK_UART11 156 165 #define PCLK_SPI0 157 166 #define PCLK_SPI1 158 167 #define PCLK_SPI2 159 168 #define PCLK_SPI3 160 169 #define PCLK_SPI4 161 170 #define CLK_SPI0 162 171 #define CLK_SPI1 163 172 #define CLK_SPI2 164 173 #define CLK_SPI3 165 174 #define CLK_SPI4 166 175 #define PCLK_WDT0 167 176 #define TCLK_WDT0 168 177 #define PCLK_PWM1 169 178 #define CLK_PWM1 170 179 #define CLK_OSC_PWM1 171 180 #define CLK_RC_PWM1 172 181 #define PCLK_BUSTIMER0 173 182 #define PCLK_BUSTIMER1 174 183 #define CLK_TIMER0_ROOT 175 184 #define CLK_TIMER0 176 185 #define CLK_TIMER1 177 186 #define CLK_TIMER2 178 187 #define CLK_TIMER3 179 188 #define CLK_TIMER4 180 189 #define CLK_TIMER5 181 190 #define PCLK_MAILBOX0 182 191 #define PCLK_GPIO1 183 192 #define DBCLK_GPIO1 184 193 #define PCLK_GPIO2 185 194 #define DBCLK_GPIO2 186 195 #define PCLK_GPIO3 187 196 #define DBCLK_GPIO3 188 197 #define PCLK_GPIO4 189 198 #define DBCLK_GPIO4 190 199 #define ACLK_DECOM 191 200 #define PCLK_DECOM 192 201 #define DCLK_DECOM 193 202 #define CLK_TIMER1_ROOT 194 203 #define CLK_TIMER6 195 204 #define CLK_TIMER7 196 205 #define CLK_TIMER8 197 206 #define CLK_TIMER9 198 207 #define CLK_TIMER10 199 208 #define CLK_TIMER11 200 209 #define ACLK_DMAC0 201 210 #define ACLK_DMAC1 202 211 #define ACLK_DMAC2 203 212 #define ACLK_SPINLOCK 204 213 #define HCLK_I3C0 205 214 #define HCLK_I3C1 206 215 #define HCLK_BUS_CM0_ROOT 207 216 #define FCLK_BUS_CM0_CORE 208 217 #define CLK_BUS_CM0_RTC 209 218 #define PCLK_PMU2 210 219 #define PCLK_PWM2 211 220 #define CLK_PWM2 212 221 #define CLK_RC_PWM2 213 222 #define CLK_OSC_PWM2 214 223 #define CLK_FREQ_PWM1 215 224 #define CLK_COUNTER_PWM1 216 225 #define SAI_SCLKIN_FREQ 217 226 #define SAI_SCLKIN_COUNTER 218 227 #define CLK_I3C0 219 228 #define CLK_I3C1 220 229 #define PCLK_CSIDPHY1 221 230 #define PCLK_DDR_ROOT 222 231 #define PCLK_DDR_MON_CH0 223 232 #define TMCLK_DDR_MON_CH0 224 233 #define ACLK_DDR_ROOT 225 234 #define HCLK_DDR_ROOT 226 235 #define FCLK_DDR_CM0_CORE 227 236 #define CLK_DDR_TIMER_ROOT 228 237 #define CLK_DDR_TIMER0 229 238 #define CLK_DDR_TIMER1 230 239 #define TCLK_WDT_DDR 231 240 #define PCLK_WDT 232 241 #define PCLK_TIMER 233 242 #define CLK_DDR_CM0_RTC 234 243 #define ACLK_RKNN0 235 244 #define ACLK_RKNN1 236 245 #define HCLK_RKNN_ROOT 237 246 #define CLK_RKNN_DSU0 238 247 #define PCLK_NPUTOP_ROOT 239 248 #define PCLK_NPU_TIMER 240 249 #define CLK_NPUTIMER_ROOT 241 250 #define CLK_NPUTIMER0 242 251 #define CLK_NPUTIMER1 243 252 #define PCLK_NPU_WDT 244 253 #define TCLK_NPU_WDT 245 254 #define ACLK_RKNN_CBUF 246 255 #define HCLK_NPU_CM0_ROOT 247 256 #define FCLK_NPU_CM0_CORE 248 257 #define CLK_NPU_CM0_RTC 249 258 #define HCLK_RKNN_CBUF 250 259 #define HCLK_NVM_ROOT 251 260 #define ACLK_NVM_ROOT 252 261 #define SCLK_FSPI_X2 253 262 #define HCLK_FSPI 254 263 #define CCLK_SRC_EMMC 255 264 #define HCLK_EMMC 256 265 #define ACLK_EMMC 257 266 #define BCLK_EMMC 258 267 #define TCLK_EMMC 259 268 #define PCLK_PHP_ROOT 260 269 #define ACLK_PHP_ROOT 261 270 #define PCLK_PCIE0 262 271 #define CLK_PCIE0_AUX 263 272 #define ACLK_PCIE0_MST 264 273 #define ACLK_PCIE0_SLV 265 274 #define ACLK_PCIE0_DBI 266 275 #define ACLK_USB3OTG1 267 276 #define CLK_REF_USB3OTG1 268 277 #define CLK_SUSPEND_USB3OTG1 269 278 #define ACLK_MMU0 270 279 #define ACLK_SLV_MMU0 271 280 #define ACLK_MMU1 272 281 #define ACLK_SLV_MMU1 273 282 #define PCLK_PCIE1 275 283 #define CLK_PCIE1_AUX 276 284 #define ACLK_PCIE1_MST 277 285 #define ACLK_PCIE1_SLV 278 286 #define ACLK_PCIE1_DBI 279 287 #define CLK_RXOOB0 280 288 #define CLK_RXOOB1 281 289 #define CLK_PMALIVE0 282 290 #define CLK_PMALIVE1 283 291 #define ACLK_SATA0 284 292 #define ACLK_SATA1 285 293 #define CLK_USB3OTG1_PIPE_PCLK 286 294 #define CLK_USB3OTG1_UTMI 287 295 #define CLK_USB3OTG0_PIPE_PCLK 288 296 #define CLK_USB3OTG0_UTMI 289 297 #define HCLK_SDGMAC_ROOT 290 298 #define ACLK_SDGMAC_ROOT 291 299 #define PCLK_SDGMAC_ROOT 292 300 #define ACLK_GMAC0 293 301 #define ACLK_GMAC1 294 302 #define PCLK_GMAC0 295 303 #define PCLK_GMAC1 296 304 #define CCLK_SRC_SDIO 297 305 #define HCLK_SDIO 298 306 #define CLK_GMAC1_PTP_REF 299 307 #define CLK_GMAC0_PTP_REF 300 308 #define CLK_GMAC1_PTP_REF_SRC 301 309 #define CLK_GMAC0_PTP_REF_SRC 302 310 #define CCLK_SRC_SDMMC0 303 311 #define HCLK_SDMMC0 304 312 #define SCLK_FSPI1_X2 305 313 #define HCLK_FSPI1 306 314 #define ACLK_DSMC_ROOT 307 315 #define ACLK_DSMC 308 316 #define PCLK_DSMC 309 317 #define CLK_DSMC_SYS 310 318 #define HCLK_HSGPIO 311 319 #define CLK_HSGPIO_TX 312 320 #define CLK_HSGPIO_RX 313 321 #define ACLK_HSGPIO 314 322 #define PCLK_PHPPHY_ROOT 315 323 #define PCLK_PCIE2_COMBOPHY0 316 324 #define PCLK_PCIE2_COMBOPHY1 317 325 #define CLK_PCIE_100M_SRC 318 326 #define CLK_PCIE_100M_NDUTY_SRC 319 327 #define CLK_REF_PCIE0_PHY 320 328 #define CLK_REF_PCIE1_PHY 321 329 #define CLK_REF_MPHY_26M 322 330 #define HCLK_RKVDEC_ROOT 323 331 #define ACLK_RKVDEC_ROOT 324 332 #define HCLK_RKVDEC 325 333 #define CLK_RKVDEC_HEVC_CA 326 334 #define CLK_RKVDEC_CORE 327 335 #define ACLK_UFS_ROOT 328 336 #define ACLK_USB_ROOT 329 337 #define PCLK_USB_ROOT 330 338 #define ACLK_USB3OTG0 331 339 #define CLK_REF_USB3OTG0 332 340 #define CLK_SUSPEND_USB3OTG0 333 341 #define ACLK_MMU2 334 342 #define ACLK_SLV_MMU2 335 343 #define ACLK_UFS_SYS 336 344 #define ACLK_VPU_ROOT 337 345 #define ACLK_VPU_MID_ROOT 338 346 #define HCLK_VPU_ROOT 339 347 #define ACLK_JPEG_ROOT 340 348 #define ACLK_VPU_LOW_ROOT 341 349 #define HCLK_RGA2E_0 342 350 #define ACLK_RGA2E_0 342 351 #define CLK_CORE_RGA2E_0 344 352 #define ACLK_JPEG 345 353 #define HCLK_JPEG 346 354 #define HCLK_VDPP 347 355 #define ACLK_VDPP 348 356 #define CLK_CORE_VDPP 349 357 #define HCLK_RGA2E_1 350 358 #define ACLK_RGA2E_1 351 359 #define CLK_CORE_RGA2E_1 352 360 #define DCLK_EBC_FRAC_SRC 353 361 #define HCLK_EBC 354 362 #define ACLK_EBC 355 363 #define DCLK_EBC 356 364 #define HCLK_VEPU0_ROOT 357 365 #define ACLK_VEPU0_ROOT 358 366 #define HCLK_VEPU0 359 367 #define ACLK_VEPU0 360 368 #define CLK_VEPU0_CORE 361 369 #define ACLK_VI_ROOT 362 370 #define HCLK_VI_ROOT 363 371 #define PCLK_VI_ROOT 364 372 #define DCLK_VICAP 365 373 #define ACLK_VICAP 366 374 #define HCLK_VICAP 367 375 #define CLK_ISP_CORE 368 376 #define CLK_ISP_CORE_MARVIN 369 377 #define CLK_ISP_CORE_VICAP 370 378 #define ACLK_ISP 371 379 #define HCLK_ISP 372 380 #define ACLK_VPSS 373 381 #define HCLK_VPSS 374 382 #define CLK_CORE_VPSS 375 383 #define PCLK_CSI_HOST_0 376 384 #define PCLK_CSI_HOST_1 377 385 #define PCLK_CSI_HOST_2 378 386 #define PCLK_CSI_HOST_3 379 387 #define PCLK_CSI_HOST_4 380 388 #define ICLK_CSIHOST01 381 389 #define ICLK_CSIHOST0 382 390 #define CLK_ISP_PVTPLL_SRC 383 391 #define ACLK_VI_ROOT_INTER 384 392 #define CLK_VICAP_I0CLK 385 393 #define CLK_VICAP_I1CLK 386 394 #define CLK_VICAP_I2CLK 387 395 #define CLK_VICAP_I3CLK 388 396 #define CLK_VICAP_I4CLK 389 397 #define ACLK_VOP_ROOT 390 398 #define HCLK_VOP_ROOT 391 399 #define PCLK_VOP_ROOT 392 400 #define HCLK_VOP 393 401 #define ACLK_VOP 394 402 #define DCLK_VP0_SRC 395 403 #define DCLK_VP1_SRC 396 404 #define DCLK_VP2_SRC 397 405 #define DCLK_VP0 398 406 #define DCLK_VP1 400 407 #define DCLK_VP2 401 408 #define PCLK_VOPGRF 402 409 #define ACLK_VO0_ROOT 403 410 #define HCLK_VO0_ROOT 404 411 #define PCLK_VO0_ROOT 405 412 #define PCLK_VO0_GRF 406 413 #define ACLK_HDCP0 407 414 #define HCLK_HDCP0 408 415 #define PCLK_HDCP0 409 416 #define CLK_TRNG0_SKP 410 417 #define PCLK_DSIHOST0 411 418 #define CLK_DSIHOST0 412 419 #define PCLK_HDMITX0 413 420 #define CLK_HDMITX0_EARC 414 421 #define CLK_HDMITX0_REF 415 422 #define PCLK_EDP0 416 423 #define CLK_EDP0_24M 417 424 #define CLK_EDP0_200M 418 425 #define MCLK_SAI5_8CH_SRC 419 426 #define MCLK_SAI5_8CH 420 427 #define HCLK_SAI5_8CH 421 428 #define MCLK_SAI6_8CH_SRC 422 429 #define MCLK_SAI6_8CH 423 430 #define HCLK_SAI6_8CH 424 431 #define HCLK_SPDIF_TX2 425 432 #define MCLK_SPDIF_TX2 426 433 #define HCLK_SPDIF_RX2 427 434 #define MCLK_SPDIF_RX2 428 435 #define HCLK_SAI8_8CH 429 436 #define MCLK_SAI8_8CH_SRC 430 437 #define MCLK_SAI8_8CH 431 438 #define ACLK_VO1_ROOT 432 439 #define HCLK_VO1_ROOT 433 440 #define PCLK_VO1_ROOT 434 441 #define MCLK_SAI7_8CH_SRC 435 442 #define MCLK_SAI7_8CH 436 443 #define HCLK_SAI7_8CH 437 444 #define HCLK_SPDIF_TX3 438 445 #define HCLK_SPDIF_TX4 439 446 #define HCLK_SPDIF_TX5 440 447 #define MCLK_SPDIF_TX3 441 448 #define CLK_AUX16MHZ_0 442 449 #define ACLK_DP0 443 450 #define PCLK_DP0 444 451 #define PCLK_VO1_GRF 445 452 #define ACLK_HDCP1 446 453 #define HCLK_HDCP1 447 454 #define PCLK_HDCP1 448 455 #define CLK_TRNG1_SKP 449 456 #define HCLK_SAI9_8CH 450 457 #define MCLK_SAI9_8CH_SRC 451 458 #define MCLK_SAI9_8CH 452 459 #define MCLK_SPDIF_TX4 453 460 #define MCLK_SPDIF_TX5 454 461 #define CLK_GPU_SRC_PRE 455 462 #define CLK_GPU 456 463 #define PCLK_GPU_ROOT 457 464 #define ACLK_CENTER_ROOT 458 465 #define ACLK_CENTER_LOW_ROOT 459 466 #define HCLK_CENTER_ROOT 460 467 #define PCLK_CENTER_ROOT 461 468 #define ACLK_DMA2DDR 462 469 #define ACLK_DDR_SHAREMEM 463 470 #define PCLK_DMA2DDR 464 471 #define PCLK_SHAREMEM 465 472 #define HCLK_VEPU1_ROOT 466 473 #define ACLK_VEPU1_ROOT 467 474 #define HCLK_VEPU1 468 475 #define ACLK_VEPU1 469 476 #define CLK_VEPU1_CORE 470 477 #define CLK_JDBCK_DAP 471 478 #define PCLK_MIPI_DCPHY 472 479 #define CLK_32K_USB2DEBUG 473 480 #define PCLK_CSIDPHY 474 481 #define PCLK_USBDPPHY 475 482 #define CLK_PMUPHY_REF_SRC 476 483 #define CLK_USBDP_COMBO_PHY_IMMORTAL 477 484 #define CLK_HDMITXHPD 478 485 #define PCLK_MPHY 479 486 #define CLK_REF_OSC_MPHY 480 487 #define CLK_REF_UFS_CLKOUT 481 488 #define HCLK_PMU1_ROOT 482 489 #define HCLK_PMU_CM0_ROOT 483 490 #define CLK_200M_PMU_SRC 484 491 #define CLK_100M_PMU_SRC 485 492 #define CLK_50M_PMU_SRC 486 493 #define FCLK_PMU_CM0_CORE 487 494 #define CLK_PMU_CM0_RTC 488 495 #define PCLK_PMU1 489 496 #define CLK_PMU1 490 497 #define PCLK_PMU1WDT 491 498 #define TCLK_PMU1WDT 492 499 #define PCLK_PMUTIMER 493 500 #define CLK_PMUTIMER_ROOT 494 501 #define CLK_PMUTIMER0 495 502 #define CLK_PMUTIMER1 496 503 #define PCLK_PMU1PWM 497 504 #define CLK_PMU1PWM 498 505 #define CLK_PMU1PWM_OSC 499 506 #define PCLK_PMUPHY_ROOT 500 507 #define PCLK_I2C0 501 508 #define CLK_I2C0 502 509 #define SCLK_UART1 503 510 #define PCLK_UART1 504 511 #define CLK_PMU1PWM_RC 505 512 #define CLK_PDM0 506 513 #define HCLK_PDM0 507 514 #define MCLK_PDM0 508 515 #define HCLK_VAD 509 516 #define CLK_OSCCHK_PVTM 510 517 #define CLK_PDM0_OUT 511 518 #define CLK_HPTIMER_SRC 512 519 #define PCLK_PMU0_ROOT 516 520 #define PCLK_PMU0 517 521 #define PCLK_GPIO0 518 522 #define DBCLK_GPIO0 519 523 #define CLK_OSC0_PMU1 520 524 #define PCLK_PMU1_ROOT 521 525 #define XIN_OSC0_DIV 522 526 #define ACLK_USB 523 527 #define ACLK_UFS 524 528 #define ACLK_SDGMAC 525 529 #define HCLK_SDGMAC 526 530 #define PCLK_SDGMAC 527 531 #define HCLK_VO1 528 532 #define HCLK_VO0 529 533 #define PCLK_CCI_ROOT 532 534 #define ACLK_CCI_ROOT 533 535 #define HCLK_VO0VOP_CHANNEL 534 536 #define ACLK_VO0VOP_CHANNEL 535 537 #define ACLK_TOP_MID 536 538 #define ACLK_SECURE_HIGH 537 539 #define CLK_USBPHY_REF_SRC 538 540 #define CLK_PHY_REF_SRC 539 541 #define CLK_CPLL_REF_SRC 540 542 #define CLK_AUPLL_REF_SRC 541 543 #define PCLK_SECURE_NS 542 544 #define HCLK_SECURE_NS 543 545 #define ACLK_SECURE_NS 544 546 #define PCLK_OTPC_NS 545 547 #define HCLK_CRYPTO_NS 546 548 #define HCLK_TRNG_NS 547 549 #define CLK_OTPC_NS 548 550 #define SCLK_DSU 549 551 #define SCLK_DDR 550 552 #define ACLK_CRYPTO_NS 551 553 #define CLK_PKA_CRYPTO_NS 552 554 555 /* secure clk */ 556 #define CLK_STIMER0_ROOT 600 557 #define CLK_STIMER1_ROOT 601 558 #define PCLK_SECURE_S 602 559 #define HCLK_SECURE_S 603 560 #define ACLK_SECURE_S 604 561 #define CLK_PKA_CRYPTO_S 605 562 #define HCLK_VO1_S 606 563 #define PCLK_VO1_S 607 564 #define HCLK_VO0_S 608 565 #define PCLK_VO0_S 609 566 #define PCLK_KLAD 610 567 #define HCLK_CRYPTO_S 611 568 #define HCLK_KLAD 612 569 #define ACLK_CRYPTO_S 613 570 #define HCLK_TRNG_S 614 571 #define PCLK_OTPC_S 615 572 #define CLK_OTPC_S 616 573 #define PCLK_WDT_S 617 574 #define TCLK_WDT_S 618 575 #define PCLK_HDCP0_TRNG 619 576 #define PCLK_HDCP1_TRNG 620 577 #define HCLK_HDCP_KEY0 621 578 #define HCLK_HDCP_KEY1 622 579 #define PCLK_EDP_S 623 580 #define ACLK_KLAD 624 581 582 #define CLK_NR_CLKS (ACLK_KLAD + 1) 583 584 /********Name=SOFTRST_CON01,Offset=0xA04********/ 585 #define SRST_A_TOP_BIU 19 586 #define SRST_P_TOP_BIU 21 587 #define SRST_A_TOP_MID_BIU 22 588 #define SRST_A_SECURE_HIGH_BIU 23 589 #define SRST_H_TOP_BIU 30 590 /********Name=SOFTRST_CON02,Offset=0xA08********/ 591 #define SRST_H_VO0VOP_CHANNEL_BIU 32 592 #define SRST_A_VO0VOP_CHANNEL_BIU 33 593 /********Name=SOFTRST_CON06,Offset=0xA18********/ 594 #define SRST_BISRINTF 98 595 /********Name=SOFTRST_CON07,Offset=0xA1C********/ 596 #define SRST_H_AUDIO_BIU 114 597 #define SRST_H_ASRC_2CH_0 115 598 #define SRST_H_ASRC_2CH_1 116 599 #define SRST_H_ASRC_4CH_0 117 600 #define SRST_H_ASRC_4CH_1 118 601 #define SRST_ASRC_2CH_0 119 602 #define SRST_ASRC_2CH_1 120 603 #define SRST_ASRC_4CH_0 121 604 #define SRST_ASRC_4CH_1 122 605 #define SRST_M_SAI0_8CH 124 606 #define SRST_H_SAI0_8CH 125 607 #define SRST_H_SPDIF_RX0 126 608 #define SRST_M_SPDIF_RX0 127 609 /********Name=SOFTRST_CON08,Offset=0xA20********/ 610 #define SRST_H_SPDIF_RX1 128 611 #define SRST_M_SPDIF_RX1 129 612 #define SRST_M_SAI1_8CH 133 613 #define SRST_H_SAI1_8CH 134 614 #define SRST_M_SAI2_2CH 136 615 #define SRST_H_SAI2_2CH 138 616 #define SRST_M_SAI3_2CH 140 617 #define SRST_H_SAI3_2CH 142 618 /********Name=SOFTRST_CON09,Offset=0xA24********/ 619 #define SRST_M_SAI4_2CH 144 620 #define SRST_H_SAI4_2CH 146 621 #define SRST_H_ACDCDIG_DSM 147 622 #define SRST_M_ACDCDIG_DSM 148 623 #define SRST_PDM1 149 624 #define SRST_H_PDM1 151 625 #define SRST_M_PDM1 152 626 #define SRST_H_SPDIF_TX0 153 627 #define SRST_M_SPDIF_TX0 154 628 #define SRST_H_SPDIF_TX1 155 629 #define SRST_M_SPDIF_TX1 156 630 /********Name=SOFTRST_CON11,Offset=0xA2C********/ 631 #define SRST_A_BUS_BIU 179 632 #define SRST_P_BUS_BIU 180 633 #define SRST_P_CRU 181 634 #define SRST_H_CAN0 182 635 #define SRST_CAN0 183 636 #define SRST_H_CAN1 184 637 #define SRST_CAN1 185 638 #define SRST_P_INTMUX2BUS 188 639 #define SRST_P_VCCIO_IOC 189 640 #define SRST_H_BUS_BIU 190 641 #define SRST_KEY_SHIFT 191 642 /********Name=SOFTRST_CON12,Offset=0xA30********/ 643 #define SRST_P_I2C1 192 644 #define SRST_P_I2C2 193 645 #define SRST_P_I2C3 194 646 #define SRST_P_I2C4 195 647 #define SRST_P_I2C5 196 648 #define SRST_P_I2C6 197 649 #define SRST_P_I2C7 198 650 #define SRST_P_I2C8 199 651 #define SRST_P_I2C9 200 652 #define SRST_P_WDT_BUSMCU 201 653 #define SRST_T_WDT_BUSMCU 202 654 #define SRST_A_GIC 203 655 #define SRST_I2C1 204 656 #define SRST_I2C2 205 657 #define SRST_I2C3 206 658 #define SRST_I2C4 207 659 /********Name=SOFTRST_CON13,Offset=0xA34********/ 660 #define SRST_I2C5 208 661 #define SRST_I2C6 209 662 #define SRST_I2C7 210 663 #define SRST_I2C8 211 664 #define SRST_I2C9 212 665 #define SRST_P_SARADC 214 666 #define SRST_SARADC 215 667 #define SRST_P_TSADC 216 668 #define SRST_TSADC 217 669 #define SRST_P_UART0 218 670 #define SRST_P_UART2 219 671 #define SRST_P_UART3 220 672 #define SRST_P_UART4 221 673 #define SRST_P_UART5 222 674 #define SRST_P_UART6 223 675 /********Name=SOFTRST_CON14,Offset=0xA38********/ 676 #define SRST_P_UART7 224 677 #define SRST_P_UART8 225 678 #define SRST_P_UART9 226 679 #define SRST_P_UART10 227 680 #define SRST_P_UART11 228 681 #define SRST_S_UART0 229 682 #define SRST_S_UART2 230 683 #define SRST_S_UART3 233 684 #define SRST_S_UART4 236 685 #define SRST_S_UART5 239 686 /********Name=SOFTRST_CON15,Offset=0xA3C********/ 687 #define SRST_S_UART6 242 688 #define SRST_S_UART7 245 689 #define SRST_S_UART8 248 690 #define SRST_S_UART9 249 691 #define SRST_S_UART10 250 692 #define SRST_S_UART11 251 693 #define SRST_P_SPI0 253 694 #define SRST_P_SPI1 254 695 #define SRST_P_SPI2 255 696 /********Name=SOFTRST_CON16,Offset=0xA40********/ 697 #define SRST_P_SPI3 256 698 #define SRST_P_SPI4 257 699 #define SRST_SPI0 258 700 #define SRST_SPI1 259 701 #define SRST_SPI2 260 702 #define SRST_SPI3 261 703 #define SRST_SPI4 262 704 #define SRST_P_WDT0 263 705 #define SRST_T_WDT0 264 706 #define SRST_P_SYS_GRF 265 707 #define SRST_P_PWM1 266 708 #define SRST_PWM1 267 709 710 /********Name=SOFTRST_CON17,Offset=0xA44********/ 711 #define SRST_P_BUSTIMER0 275 712 #define SRST_P_BUSTIMER1 276 713 #define SRST_TIMER0 278 714 #define SRST_TIMER1 279 715 #define SRST_TIMER2 280 716 #define SRST_TIMER3 281 717 #define SRST_TIMER4 282 718 #define SRST_TIMER5 283 719 #define SRST_P_BUSIOC 284 720 #define SRST_P_MAILBOX0 285 721 #define SRST_P_GPIO1 287 722 /********Name=SOFTRST_CON18,Offset=0xA48********/ 723 #define SRST_GPIO1 288 724 #define SRST_P_GPIO2 289 725 #define SRST_GPIO2 290 726 #define SRST_P_GPIO3 291 727 #define SRST_GPIO3 292 728 #define SRST_P_GPIO4 293 729 #define SRST_GPIO4 294 730 #define SRST_A_DECOM 295 731 #define SRST_P_DECOM 296 732 #define SRST_D_DECOM 297 733 #define SRST_TIMER6 299 734 #define SRST_TIMER7 300 735 #define SRST_TIMER8 301 736 #define SRST_TIMER9 302 737 #define SRST_TIMER10 303 738 /********Name=SOFTRST_CON19,Offset=0xA4C********/ 739 #define SRST_TIMER11 304 740 #define SRST_A_DMAC0 305 741 #define SRST_A_DMAC1 306 742 #define SRST_A_DMAC2 307 743 #define SRST_A_SPINLOCK 308 744 #define SRST_REF_PVTPLL_BUS 309 745 #define SRST_H_I3C0 311 746 #define SRST_H_I3C1 313 747 #define SRST_H_BUS_CM0_BIU 315 748 #define SRST_F_BUS_CM0_CORE 316 749 #define SRST_T_BUS_CM0_JTAG 317 750 /********Name=SOFTRST_CON20,Offset=0xA50********/ 751 #define SRST_P_INTMUX2PMU 320 752 #define SRST_P_INTMUX2DDR 321 753 #define SRST_P_PVTPLL_BUS 323 754 #define SRST_P_PWM2 324 755 #define SRST_PWM2 325 756 #define SRST_FREQ_PWM1 328 757 #define SRST_COUNTER_PWM1 329 758 #define SRST_I3C0 332 759 #define SRST_I3C1 333 760 /********Name=SOFTRST_CON21,Offset=0xA54********/ 761 #define SRST_P_DDR_MON_CH0 337 762 #define SRST_P_DDR_BIU 338 763 #define SRST_P_DDR_UPCTL_CH0 339 764 #define SRST_TM_DDR_MON_CH0 340 765 #define SRST_A_DDR_BIU 341 766 #define SRST_DFI_CH0 342 767 #define SRST_DDR_MON_CH0 346 768 #define SRST_P_DDR_HWLP_CH0 349 769 #define SRST_P_DDR_MON_CH1 350 770 #define SRST_P_DDR_HWLP_CH1 351 771 /********Name=SOFTRST_CON22,Offset=0xA58********/ 772 #define SRST_P_DDR_UPCTL_CH1 352 773 #define SRST_TM_DDR_MON_CH1 353 774 #define SRST_DFI_CH1 354 775 #define SRST_A_DDR01_MSCH0 355 776 #define SRST_A_DDR01_MSCH1 356 777 #define SRST_DDR_MON_CH1 358 778 #define SRST_DDR_SCRAMBLE_CH0 361 779 #define SRST_DDR_SCRAMBLE_CH1 362 780 #define SRST_P_AHB2APB 364 781 #define SRST_H_AHB2APB 365 782 #define SRST_H_DDR_BIU 366 783 #define SRST_F_DDR_CM0_CORE 367 784 /********Name=SOFTRST_CON23,Offset=0xA5C********/ 785 #define SRST_P_DDR01_MSCH0 369 786 #define SRST_P_DDR01_MSCH1 370 787 #define SRST_DDR_TIMER0 372 788 #define SRST_DDR_TIMER1 373 789 #define SRST_T_WDT_DDR 374 790 #define SRST_P_WDT 375 791 #define SRST_P_TIMER 376 792 #define SRST_T_DDR_CM0_JTAG 377 793 #define SRST_P_DDR_GRF 379 794 /********Name=SOFTRST_CON25,Offset=0xA64********/ 795 #define SRST_DDR_UPCTL_CH0 401 796 #define SRST_A_DDR_UPCTL_0_CH0 402 797 #define SRST_A_DDR_UPCTL_1_CH0 403 798 #define SRST_A_DDR_UPCTL_2_CH0 404 799 #define SRST_A_DDR_UPCTL_3_CH0 405 800 #define SRST_A_DDR_UPCTL_4_CH0 406 801 /********Name=SOFTRST_CON26,Offset=0xA68********/ 802 #define SRST_DDR_UPCTL_CH1 417 803 #define SRST_A_DDR_UPCTL_0_CH1 418 804 #define SRST_A_DDR_UPCTL_1_CH1 419 805 #define SRST_A_DDR_UPCTL_2_CH1 420 806 #define SRST_A_DDR_UPCTL_3_CH1 421 807 #define SRST_A_DDR_UPCTL_4_CH1 422 808 /********Name=SOFTRST_CON27,Offset=0xA6C********/ 809 #define SRST_REF_PVTPLL_DDR 432 810 #define SRST_P_PVTPLL_DDR 433 811 812 /********Name=SOFTRST_CON28,Offset=0xA70********/ 813 #define SRST_A_RKNN0 457 814 #define SRST_A_RKNN0_BIU 459 815 #define SRST_L_RKNN0_BIU 460 816 /********Name=SOFTRST_CON29,Offset=0xA74********/ 817 #define SRST_A_RKNN1 464 818 #define SRST_A_RKNN1_BIU 466 819 #define SRST_L_RKNN1_BIU 467 820 /********Name=SOFTRST_CON31,Offset=0xA7C********/ 821 #define SRST_NPU_DAP 496 822 #define SRST_L_NPUSUBSYS_BIU 497 823 #define SRST_P_NPUTOP_BIU 505 824 #define SRST_P_NPU_TIMER 506 825 #define SRST_NPUTIMER0 508 826 #define SRST_NPUTIMER1 509 827 #define SRST_P_NPU_WDT 510 828 #define SRST_T_NPU_WDT 511 829 /********Name=SOFTRST_CON32,Offset=0xA80********/ 830 #define SRST_A_RKNN_CBUF 512 831 #define SRST_A_RVCORE0 513 832 #define SRST_P_NPU_GRF 514 833 #define SRST_P_PVTPLL_NPU 515 834 #define SRST_NPU_PVTPLL 516 835 #define SRST_H_NPU_CM0_BIU 518 836 #define SRST_F_NPU_CM0_CORE 519 837 #define SRST_T_NPU_CM0_JTAG 520 838 #define SRST_A_RKNNTOP_BIU 523 839 #define SRST_H_RKNN_CBUF 524 840 #define SRST_H_RKNNTOP_BIU 525 841 /********Name=SOFTRST_CON33,Offset=0xA84********/ 842 #define SRST_H_NVM_BIU 530 843 #define SRST_A_NVM_BIU 531 844 #define SRST_S_FSPI 534 845 #define SRST_H_FSPI 535 846 #define SRST_C_EMMC 536 847 #define SRST_H_EMMC 537 848 #define SRST_A_EMMC 538 849 #define SRST_B_EMMC 539 850 #define SRST_T_EMMC 540 851 /********Name=SOFTRST_CON34,Offset=0xA88********/ 852 #define SRST_P_GRF 545 853 #define SRST_P_PHP_BIU 549 854 #define SRST_A_PHP_BIU 553 855 #define SRST_P_PCIE0 557 856 #define SRST_PCIE0_POWER_UP 559 857 /********Name=SOFTRST_CON35,Offset=0xA8C********/ 858 #define SRST_A_USB3OTG1 563 859 #define SRST_A_MMU0 571 860 #define SRST_A_SLV_MMU0 573 861 #define SRST_A_MMU1 574 862 /********Name=SOFTRST_CON36,Offset=0xA90********/ 863 #define SRST_A_SLV_MMU1 576 864 #define SRST_P_PCIE1 583 865 #define SRST_PCIE1_POWER_UP 585 866 /********Name=SOFTRST_CON37,Offset=0xA94********/ 867 #define SRST_RXOOB0 592 868 #define SRST_RXOOB1 593 869 #define SRST_PMALIVE0 594 870 #define SRST_PMALIVE1 595 871 #define SRST_A_SATA0 596 872 #define SRST_A_SATA1 597 873 #define SRST_ASIC1 598 874 #define SRST_ASIC0 599 875 /********Name=SOFTRST_CON40,Offset=0xAA0********/ 876 #define SRST_P_CSIDPHY1 642 877 #define SRST_SCAN_CSIDPHY1 643 878 /********Name=SOFTRST_CON42,Offset=0xAA8********/ 879 #define SRST_P_SDGMAC_GRF 675 880 #define SRST_P_SDGMAC_BIU 676 881 #define SRST_A_SDGMAC_BIU 677 882 #define SRST_H_SDGMAC_BIU 678 883 #define SRST_A_GMAC0 679 884 #define SRST_A_GMAC1 680 885 #define SRST_P_GMAC0 681 886 #define SRST_P_GMAC1 682 887 #define SRST_H_SDIO 684 888 /********Name=SOFTRST_CON43,Offset=0xAAC********/ 889 #define SRST_H_SDMMC0 690 890 #define SRST_S_FSPI1 691 891 #define SRST_H_FSPI1 692 892 #define SRST_A_DSMC_BIU 694 893 #define SRST_A_DSMC 695 894 #define SRST_P_DSMC 696 895 #define SRST_H_HSGPIO 698 896 #define SRST_HSGPIO 699 897 #define SRST_A_HSGPIO 701 898 /********Name=SOFTRST_CON45,Offset=0xAB4********/ 899 #define SRST_H_RKVDEC 723 900 #define SRST_H_RKVDEC_BIU 725 901 #define SRST_A_RKVDEC_BIU 726 902 #define SRST_RKVDEC_HEVC_CA 728 903 #define SRST_RKVDEC_CORE 729 904 /********Name=SOFTRST_CON47,Offset=0xABC********/ 905 #define SRST_A_USB_BIU 755 906 #define SRST_P_USBUFS_BIU 756 907 #define SRST_A_USB3OTG0 757 908 #define SRST_A_UFS_BIU 762 909 #define SRST_A_MMU2 764 910 #define SRST_A_SLV_MMU2 765 911 #define SRST_A_UFS_SYS 767 912 /********Name=SOFTRST_CON48,Offset=0xAC0********/ 913 #define SRST_A_UFS 768 914 #define SRST_P_USBUFS_GRF 769 915 #define SRST_P_UFS_GRF 770 916 /********Name=SOFTRST_CON49,Offset=0xAC4********/ 917 #define SRST_H_VPU_BIU 790 918 #define SRST_A_JPEG_BIU 791 919 #define SRST_A_RGA_BIU 794 920 #define SRST_A_VDPP_BIU 795 921 #define SRST_A_EBC_BIU 796 922 #define SRST_H_RGA2E_0 797 923 #define SRST_A_RGA2E_0 798 924 #define SRST_CORE_RGA2E_0 799 925 /********Name=SOFTRST_CON50,Offset=0xAC8********/ 926 #define SRST_A_JPEG 800 927 #define SRST_H_JPEG 801 928 #define SRST_H_VDPP 802 929 #define SRST_A_VDPP 803 930 #define SRST_CORE_VDPP 804 931 #define SRST_H_RGA2E_1 805 932 #define SRST_A_RGA2E_1 806 933 #define SRST_CORE_RGA2E_1 807 934 #define SRST_H_EBC 810 935 #define SRST_A_EBC 811 936 #define SRST_D_EBC 812 937 /********Name=SOFTRST_CON51,Offset=0xACC********/ 938 #define SRST_H_VEPU0_BIU 818 939 #define SRST_A_VEPU0_BIU 819 940 #define SRST_H_VEPU0 820 941 #define SRST_A_VEPU0 821 942 #define SRST_VEPU0_CORE 822 943 /********Name=SOFTRST_CON53,Offset=0xAD4********/ 944 #define SRST_A_VI_BIU 851 945 #define SRST_H_VI_BIU 852 946 #define SRST_P_VI_BIU 853 947 #define SRST_D_VICAP 854 948 #define SRST_A_VICAP 855 949 #define SRST_H_VICAP 856 950 #define SRST_ISP0 858 951 #define SRST_ISP0_VICAP 859 952 /********Name=SOFTRST_CON54,Offset=0xAD8********/ 953 #define SRST_CORE_VPSS 865 954 #define SRST_P_CSI_HOST_0 868 955 #define SRST_P_CSI_HOST_1 869 956 #define SRST_P_CSI_HOST_2 870 957 #define SRST_P_CSI_HOST_3 871 958 #define SRST_P_CSI_HOST_4 872 959 /********Name=SOFTRST_CON59,Offset=0xAEC********/ 960 #define SRST_CIFIN 944 961 #define SRST_VICAP_I0CLK 945 962 #define SRST_VICAP_I1CLK 946 963 #define SRST_VICAP_I2CLK 947 964 #define SRST_VICAP_I3CLK 948 965 #define SRST_VICAP_I4CLK 949 966 /********Name=SOFTRST_CON61,Offset=0xAF4********/ 967 #define SRST_A_VOP_BIU 980 968 #define SRST_A_VOP2_BIU 981 969 #define SRST_H_VOP_BIU 982 970 #define SRST_P_VOP_BIU 983 971 #define SRST_H_VOP 984 972 #define SRST_A_VOP 985 973 #define SRST_D_VP0 989 974 /********Name=SOFTRST_CON62,Offset=0xAF8********/ 975 #define SRST_D_VP1 992 976 #define SRST_D_VP2 993 977 #define SRST_P_VOP2_BIU 994 978 #define SRST_P_VOPGRF 995 979 /********Name=SOFTRST_CON63,Offset=0xAFC********/ 980 #define SRST_H_VO0_BIU 1013 981 #define SRST_P_VO0_BIU 1015 982 #define SRST_A_HDCP0_BIU 1017 983 #define SRST_P_VO0_GRF 1018 984 #define SRST_A_HDCP0 1020 985 #define SRST_H_HDCP0 1021 986 #define SRST_HDCP0 1022 987 /********Name=SOFTRST_CON64,Offset=0xB00********/ 988 #define SRST_P_DSIHOST0 1029 989 #define SRST_DSIHOST0 1030 990 #define SRST_P_HDMITX0 1031 991 #define SRST_HDMITX0_REF 1033 992 #define SRST_P_EDP0 1037 993 #define SRST_EDP0_24M 1038 994 /********Name=SOFTRST_CON65,Offset=0xB04********/ 995 #define SRST_M_SAI5_8CH 1044 996 #define SRST_H_SAI5_8CH 1045 997 #define SRST_M_SAI6_8CH 1048 998 #define SRST_H_SAI6_8CH 1049 999 #define SRST_H_SPDIF_TX2 1050 1000 #define SRST_M_SPDIF_TX2 1053 1001 #define SRST_H_SPDIF_RX2 1054 1002 #define SRST_M_SPDIF_RX2 1055 1003 /********Name=SOFTRST_CON66,Offset=0xB08********/ 1004 #define SRST_H_SAI8_8CH 1056 1005 #define SRST_M_SAI8_8CH 1058 1006 /********Name=SOFTRST_CON67,Offset=0xB0C********/ 1007 #define SRST_H_VO1_BIU 1077 1008 #define SRST_P_VO1_BIU 1078 1009 #define SRST_M_SAI7_8CH 1081 1010 #define SRST_H_SAI7_8CH 1082 1011 #define SRST_H_SPDIF_TX3 1083 1012 #define SRST_H_SPDIF_TX4 1084 1013 #define SRST_H_SPDIF_TX5 1085 1014 #define SRST_M_SPDIF_TX3 1086 1015 /********Name=SOFTRST_CON68,Offset=0xB10********/ 1016 #define SRST_DP0 1088 1017 #define SRST_P_VO1_GRF 1090 1018 #define SRST_A_HDCP1_BIU 1091 1019 #define SRST_A_HDCP1 1092 1020 #define SRST_H_HDCP1 1093 1021 #define SRST_HDCP1 1094 1022 #define SRST_H_SAI9_8CH 1097 1023 #define SRST_M_SAI9_8CH 1099 1024 #define SRST_M_SPDIF_TX4 1100 1025 #define SRST_M_SPDIF_TX5 1101 1026 /********Name=SOFTRST_CON69,Offset=0xB14********/ 1027 #define SRST_GPU 1107 1028 #define SRST_A_S_GPU_BIU 1110 1029 #define SRST_A_M0_GPU_BIU 1111 1030 #define SRST_P_GPU_BIU 1113 1031 #define SRST_P_GPU_GRF 1117 1032 #define SRST_GPU_PVTPLL 1118 1033 #define SRST_P_PVTPLL_GPU 1119 1034 /********Name=SOFTRST_CON72,Offset=0xB20********/ 1035 #define SRST_A_CENTER_BIU 1156 1036 #define SRST_A_DMA2DDR 1157 1037 #define SRST_A_DDR_SHAREMEM 1158 1038 #define SRST_A_DDR_SHAREMEM_BIU 1159 1039 #define SRST_H_CENTER_BIU 1160 1040 #define SRST_P_CENTER_GRF 1161 1041 #define SRST_P_DMA2DDR 1162 1042 #define SRST_P_SHAREMEM 1163 1043 #define SRST_P_CENTER_BIU 1164 1044 /********Name=SOFTRST_CON75,Offset=0xB2C********/ 1045 #define SRST_LINKSYM_HDMITXPHY0 1201 1046 /********Name=SOFTRST_CON78,Offset=0xB38********/ 1047 #define SRST_DP0_PIXELCLK 1249 1048 #define SRST_PHY_DP0_TX 1250 1049 #define SRST_DP1_PIXELCLK 1251 1050 #define SRST_DP2_PIXELCLK 1252 1051 /********Name=SOFTRST_CON79,Offset=0xB3C********/ 1052 #define SRST_H_VEPU1_BIU 1265 1053 #define SRST_A_VEPU1_BIU 1266 1054 #define SRST_H_VEPU1 1267 1055 #define SRST_A_VEPU1 1268 1056 #define SRST_VEPU1_CORE 1269 1057 1058 /********Name=PHPPHYSOFTRST_CON00,Offset=0x8A00********/ 1059 #define SRST_P_PHPPHY_CRU 131073 1060 #define SRST_P_APB2ASB_SLV_CHIP_TOP 131075 1061 #define SRST_P_PCIE2_COMBOPHY0 131077 1062 #define SRST_P_PCIE2_COMBOPHY0_GRF 131078 1063 #define SRST_P_PCIE2_COMBOPHY1 131079 1064 #define SRST_P_PCIE2_COMBOPHY1_GRF 131080 1065 /********Name=PHPPHYSOFTRST_CON01,Offset=0x8A04********/ 1066 #define SRST_PCIE0_PIPE_PHY 131093 1067 #define SRST_PCIE1_PIPE_PHY 131096 1068 1069 /********Name=SECURENSSOFTRST_CON00,Offset=0x10A00********/ 1070 #define SRST_H_CRYPTO_NS 262147 1071 #define SRST_H_TRNG_NS 262148 1072 #define SRST_P_OTPC_NS 262152 1073 #define SRST_OTPC_NS 262153 1074 1075 /********Name=PMU1SOFTRST_CON00,Offset=0x20A00********/ 1076 #define SRST_P_HDPTX_GRF 524288 1077 #define SRST_P_HDPTX_APB 524289 1078 #define SRST_P_MIPI_DCPHY 524290 1079 #define SRST_P_DCPHY_GRF 524291 1080 #define SRST_P_BOT0_APB2ASB 524292 1081 #define SRST_P_BOT1_APB2ASB 524293 1082 #define SRST_USB2DEBUG 524294 1083 #define SRST_P_CSIPHY_GRF 524295 1084 #define SRST_P_CSIPHY 524296 1085 #define SRST_P_USBPHY_GRF_0 524297 1086 #define SRST_P_USBPHY_GRF_1 524298 1087 #define SRST_P_USBDP_GRF 524299 1088 #define SRST_P_USBDPPHY 524300 1089 #define SRST_USBDP_COMBO_PHY_INIT 524303 1090 /********Name=PMU1SOFTRST_CON01,Offset=0x20A04********/ 1091 #define SRST_USBDP_COMBO_PHY_CMN 524304 1092 #define SRST_USBDP_COMBO_PHY_LANE 524305 1093 #define SRST_USBDP_COMBO_PHY_PCS 524306 1094 #define SRST_M_MIPI_DCPHY 524307 1095 #define SRST_S_MIPI_DCPHY 524308 1096 #define SRST_SCAN_CSIPHY 524309 1097 #define SRST_P_VCCIO6_IOC 524310 1098 #define SRST_OTGPHY_0 524311 1099 #define SRST_OTGPHY_1 524312 1100 #define SRST_HDPTX_INIT 524313 1101 #define SRST_HDPTX_CMN 524314 1102 #define SRST_HDPTX_LANE 524315 1103 #define SRST_HDMITXHPD 524317 1104 /********Name=PMU1SOFTRST_CON02,Offset=0x20A08********/ 1105 #define SRST_MPHY_INIT 524320 1106 #define SRST_P_MPHY_GRF 524321 1107 #define SRST_P_VCCIO7_IOC 524323 1108 /********Name=PMU1SOFTRST_CON03,Offset=0x20A0C********/ 1109 #define SRST_H_PMU1_BIU 524345 1110 #define SRST_P_PMU1_NIU 524346 1111 #define SRST_H_PMU_CM0_BIU 524347 1112 #define SRST_PMU_CM0_CORE 524348 1113 #define SRST_PMU_CM0_JTAG 524349 1114 /********Name=PMU1SOFTRST_CON04,Offset=0x20A10********/ 1115 #define SRST_P_CRU_PMU1 524353 1116 #define SRST_P_PMU1_GRF 524355 1117 #define SRST_P_PMU1_IOC 524356 1118 #define SRST_P_PMU1WDT 524357 1119 #define SRST_T_PMU1WDT 524358 1120 #define SRST_P_PMUTIMER 524359 1121 #define SRST_PMUTIMER0 524361 1122 #define SRST_PMUTIMER1 524362 1123 #define SRST_P_PMU1PWM 524363 1124 #define SRST_PMU1PWM 524364 1125 /********Name=PMU1SOFTRST_CON05,Offset=0x20A14********/ 1126 #define SRST_P_I2C0 524369 1127 #define SRST_I2C0 524371 1128 #define SRST_S_UART1 525373 1129 #define SRST_P_UART1 525374 1130 #define SRST_PDM0 524381 1131 #define SRST_H_PDM0 524383 1132 /********Name=PMU1SOFTRST_CON06,Offset=0xA18********/ 1133 #define SRST_M_PDM0 524384 1134 #define SRST_H_VAD 524385 1135 /********Name=PMU1SOFTRST_CON07,Offset=0x20A1C********/ 1136 #define SRST_P_PMU0GRF 524404 1137 #define SRST_P_PMU0IOC 524405 1138 #define SRST_P_GPIO0 524406 1139 #define SRST_DB_GPIO0 524407 1140 1141 #define SRST_NR_RSTS (SRST_DB_GPIO0 + 1) 1142 1143 void pvtplls_cpub_suspend(void); 1144 void pvtplls_cpub_resume(void); 1145 1146 void pvtplls_suspend(void); 1147 void pvtplls_resume(void); 1148 1149 void rockchip_clock_init(void); 1150 1151 #endif 1152