1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __PLATFORM_DEF_H__ 7 #define __PLATFORM_DEF_H__ 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <rk3576_def.h> 12 13 #define DEBUG_XLAT_TABLE 0 14 15 /******************************************************************************* 16 * Platform binary types for linking 17 ******************************************************************************/ 18 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 19 #define PLATFORM_LINKER_ARCH aarch64 20 21 /******************************************************************************* 22 * Generic platform constants 23 ******************************************************************************/ 24 25 /* Size of cacheable stacks */ 26 #if DEBUG_XLAT_TABLE 27 #define PLATFORM_STACK_SIZE 0x800 28 #elif IMAGE_BL1 29 #define PLATFORM_STACK_SIZE 0x440 30 #elif IMAGE_BL2 31 #define PLATFORM_STACK_SIZE 0x400 32 #elif IMAGE_BL31 33 #define PLATFORM_STACK_SIZE 0x800 34 #elif IMAGE_BL32 35 #define PLATFORM_STACK_SIZE 0x440 36 #endif 37 38 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 39 40 #define PLATFORM_SYSTEM_COUNT 1 41 #define PLATFORM_CLUSTER_COUNT 2 42 #define PLATFORM_CLUSTER0_CORE_COUNT 4 43 #define PLATFORM_CLUSTER1_CORE_COUNT 4 44 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 45 PLATFORM_CLUSTER0_CORE_COUNT) 46 47 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 48 PLATFORM_CLUSTER_COUNT + \ 49 PLATFORM_CORE_COUNT) 50 51 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 52 53 #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 54 55 /* 56 * This macro defines the deepest retention state possible. A higher state 57 * id will represent an invalid or a power down state. 58 */ 59 #define PLAT_MAX_RET_STATE 1 60 61 /* 62 * This macro defines the deepest power down states possible. Any state ID 63 * higher than this is invalid. 64 */ 65 #define PLAT_MAX_OFF_STATE 2 66 /******************************************************************************* 67 * Platform memory map related constants 68 ******************************************************************************/ 69 /* TF txet, ro, rw, Size: 512KB */ 70 #define TZRAM_BASE RK_DRAM_BASE 71 #define TZRAM_SIZE 0x100000 72 73 /******************************************************************************* 74 * BL31 specific defines. 75 ******************************************************************************/ 76 /* 77 * Put BL3-1 at the top of the Trusted RAM 78 */ 79 #define BL31_BASE (TZRAM_BASE + 0x40000) 80 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 81 82 /******************************************************************************* 83 * Platform specific page table and MMU setup constants 84 ******************************************************************************/ 85 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 86 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 87 88 #define ADDR_SPACE_SIZE (1ULL << 32) 89 #define MAX_XLAT_TABLES 18 90 #define MAX_MMAP_REGIONS 27 91 92 /******************************************************************************* 93 * Declarations and constants to access the mailboxes safely. Each mailbox is 94 * aligned on the biggest cache line size in the platform. This is known only 95 * to the platform as it might have a combination of integrated and external 96 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 97 * line at any cache level. They could belong to different cpus/clusters & 98 * get written while being protected by different locks causing corruption of 99 * a valid mailbox address. 100 ******************************************************************************/ 101 #define CACHE_WRITEBACK_SHIFT 6 102 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 103 104 /* 105 * Define GICD and GICC and GICR base 106 */ 107 #define PLAT_RK_GICD_BASE PLAT_GICD_BASE 108 #define PLAT_RK_GICC_BASE PLAT_GICC_BASE 109 #define PLAT_RK_GICR_BASE PLAT_GICR_BASE 110 111 #define PLAT_RK_UART_BASE RK_DBG_UART_BASE 112 #define PLAT_RK_UART_CLOCK RK_DBG_UART_CLOCK 113 #define PLAT_RK_UART_BAUDRATE RK_DBG_UART_BAUDRATE 114 115 #define PLAT_RK_PRIMARY_CPU 0x0 116 #endif /* __PLATFORM_DEF_H__ */ 117