1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __SOC_H__ 7 #define __SOC_H__ 8 9 enum pll_id { 10 APLL_ID, 11 CPLL_ID, 12 DPLL_ID, 13 GPLL_ID, 14 }; 15 16 enum cru_mode_con00 { 17 CLK_APLL, 18 CLK_CPLL, 19 CLK_GPLL, 20 CLK_DPLL, 21 }; 22 23 #define KHz 1000 24 #define MHz (1000 * KHz) 25 #define OSC_HZ (24 * MHz) 26 27 #define MCU_VALID_START_ADDRESS 0x800000 28 29 /* CRU */ 30 #define GLB_SRST_FST_CFG_VAL 0xfdb9 31 32 #define CRU_PLLS_CON(pll_id, i) ((pll_id) * 0x20 + (i) * 0x4) 33 #define CRU_PLL_CON(i) ((i) * 0x4) 34 #define CRU_MODE_CON 0x280 35 #define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 36 #define CRU_CLKSEL_CON_CNT 181 37 #define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 38 #define CRU_CLKGATE_CON_CNT 80 39 #define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 40 #define CRU_SOFTRST_CON_CNT 80 41 42 #define CRU_GLB_CNT_TH 0xc00 43 #define CRU_GLB_RST_ST 0xc04 44 #define CRU_GLB_SRST_FST 0xc08 45 #define CRU_GLB_SRST_SND 0xc0c 46 #define CRU_GLB_RST_CON 0xc10 47 #define CRU_GLB_RST_ST_NCLR 0xc14 48 #define CRU_LITCOREWFI_CON0 0xc40 49 #define CRU_BIGCOREWFI_CON0 0xc44 50 #define CRU_NON_SECURE_GT_CON0 0xc48 51 52 #define CRU_PLLCON0_M_MASK 0x3ff 53 #define CRU_PLLCON0_M_SHIFT 0 54 #define CRU_PLLCON1_P_MASK 0x3f 55 #define CRU_PLLCON1_P_SHIFT 0 56 #define CRU_PLLCON1_S_MASK 0x7 57 #define CRU_PLLCON1_S_SHIFT 6 58 #define CRU_PLLCON2_K_MASK 0xffff 59 #define CRU_PLLCON2_K_SHIFT 0 60 #define CRU_PLLCON1_PWRDOWN BIT(13) 61 #define CRU_PLLCON6_LOCK_STATUS BIT(15) 62 63 /* LCORE_CRU */ 64 #define LCORE_CRU_MODE_CON 0x280 65 #define LCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 66 #define LCORE_CRU_CLKSEL_CON_CNT 4 67 #define LCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 68 #define LCORE_CRU_CLKGATE_CON_CNT 2 69 #define LCORE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 70 #define LCORE_CRU_SOFTRST_CON_CNT 4 71 72 /* BCORE_CRU */ 73 #define BCORE_CRU_MODE_CON 0x280 74 #define BCORE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 75 #define BCORE_CRU_CLKSEL_CON_CNT 5 76 #define BCORE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 77 #define BCORE_CRU_CLKGATE_CON_CNT 3 78 #define BCORE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 79 #define BCORE_CRU_SOFTRST_CON_CNT 4 80 81 /* DDRCRU */ 82 #define DDRCRU_MODE_CON 0x280 83 #define DDRCRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 84 #define DDRCRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 85 #define DDRCRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 86 87 /* CCICRU */ 88 #define CCICRU_MODE_CON 0x280 89 #define CCICRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 90 #define CCICRU_CLKSEL_CON_CNT 10 91 #define CCICRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 92 #define CCICRU_CLKGATE_CON_CNT 7 93 #define CCICRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 94 #define CCICRU_SOFTRST_CON_CNT 7 95 96 /* CRU AUTOCS */ 97 #define CRU_AUTOCS_CON(offset) (CRU_BASE + (offset)) 98 #define CRU_AUTOCS_SEC_CON(offset) (SECURE_CRU_BASE + (offset)) 99 #define CRU_AUTOCS_CCI_CON(offset) (CCI_CRU_BASE + (offset)) 100 #define AUTOCS_EN_BIT BIT(12) 101 102 /* PHP_CRU */ 103 #define PHP_CRU_MODE_CON 0x280 104 #define PHP_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 105 #define PHP_CRU_CLKSEL_CON_CNT 2 106 #define PHP_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 107 #define PHP_CRU_CLKGATE_CON_CNT 2 108 #define PHP_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 109 #define PHP_CRU_SOFTRST_CON_CNT 2 110 111 /* SECURE CRU */ 112 #define SECURE_CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) 113 #define SECURE_CRU_CLKSEL_CON_CNT 1 114 #define SECURE_CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) 115 #define SECURE_CRU_CLKGATE_CON_CNT 1 116 #define SECURE_CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) 117 #define SECURE_CRU_SOFTRST_CON_CNT 1 118 119 /* SECURE SCRU */ 120 #define SECURE_SCRU_CLKSEL_CON(i) ((i) * 0x4 + 0x4000) 121 #define SECURE_SCRU_CLKSEL_CON_CNT 7 122 #define SECURE_SCRU_CLKGATE_CON(i) ((i) * 0x4 + 0x4028) 123 #define SECURE_SCRU_CLKGATE_CON_CNT 6 124 #define SECURE_SCRU_SOFTRST_CON(i) ((i) * 0x4 + 0x4050) 125 #define SECURE_SCRU_SOFTRST_CON_CNT 6 126 #define SECURE_SCRU_MODE_CON 0x4280 127 128 /* SYSGRF */ 129 #define SYSGRF_SOC_CON(i) ((i) * 4) 130 #define SYSGRF_SOC_STATUS 0x30 131 #define SYSGRF_NOC_CON(i) (0x40 + (i) * 4) 132 #define SYSGRF_NOC_STATUS(i) (0x60 + (i) * 4) 133 #define SYSGRF_MEM_CON(i) (0x80 + (i) * 4) 134 #define SYSGRF_STATUS0 0x140 135 #define SYSGRF_STATUS1 0x144 136 137 /* COREGRF */ 138 #define COREGRF_SOC_STATUS(i) (0x2c + (i) * 4) 139 #define COREGRF_CPU_CON(i) (0x34 + (i) * 4) 140 141 /* DDRGRF */ 142 #define DDRGRF_CHA_CON(i) ((i) * 4) 143 #define DDRGRF_CHB_CON(i) (0x100 + (i) * 4) 144 #define DDRGRF_CHA_ST(i) (0x60 + (i) * 4) 145 #define DDRGRF_CHB_ST(i) (0xb0 + (i) * 4) 146 #define DDRGRF_CON(i) (0x140 + (i) * 4) 147 148 /* CCIGRF */ 149 #define CCIGRF_CON(i) ((i) * 4) 150 #define CCIGRF_STATUS(i) (0x34 + (i) * 4) 151 152 /* IOC */ 153 #define VCCIO_IOC_MISC_CON(i) (0x400 + (i) * 4) 154 155 /* pvtm */ 156 #define PVTM_CON(i) (0x4 + (i) * 4) 157 #define PVTM_INTEN 0x70 158 #define PVTM_INTSTS 0x74 159 #define PVTM_STATUS(i) (0x80 + (i) * 4) 160 #define PVTM_CALC_CNT 0x200 161 162 enum pvtm_con0 { 163 pvtm_start = 0, 164 pvtm_osc_en = 1, 165 pvtm_osc_sel = 2, 166 pvtm_rnd_seed_en = 5, 167 }; 168 169 /* WDT */ 170 #define WDT_CR 0x0 171 #define WDT_TORR 0x4 172 #define WDT_CCVR 0x8 173 #define WDT_CRR 0xc 174 #define WDT_STAT 0x10 175 #define WDT_EOI 0x14 176 177 #define WDT_EN BIT(0) 178 #define WDT_RSP_MODE BIT(1) 179 180 /* timer */ 181 #define TIMER_LOAD_COUNT0 0x00 182 #define TIMER_LOAD_COUNT1 0x04 183 #define TIMER_CURRENT_VALUE0 0x08 184 #define TIMER_CURRENT_VALUE1 0x0c 185 #define TIMER_CONTROL_REG 0x10 186 #define TIMER_INTSTATUS 0x18 187 188 #define TIMER_DIS 0x0 189 #define TIMER_EN 0x1 190 191 #define TIMER_FMODE (0x0 << 1) 192 #define TIMER_RMODE (0x1 << 1) 193 194 /* hp timer */ 195 #define TIMER_HP_REVISION 0x00 196 #define TIMER_HP_CTRL 0x04 197 #define TIMER_HP_INTR_EN 0x08 198 #define TIMER_HP_T24_GCD 0x0c 199 #define TIMER_HP_T32_GCD 0x10 200 #define TIMER_HP_LOAD_COUNT0 0x14 201 #define TIMER_HP_LOAD_COUNT1 0x18 202 #define TIMER_HP_T24_DELAT_COUNT0 0x1c 203 #define TIMER_HP_T24_DELAT_COUNT1 0x20 204 #define TIMER_HP_CURR_32K_VALUE0 0x24 205 #define TIMER_HP_CURR_32K_VALUE1 0x28 206 #define TIMER_HP_CURR_TIMER_VALUE0 0x2c 207 #define TIMER_HP_CURR_TIMER_VALUE1 0x30 208 #define TIMER_HP_T24_32BEGIN0 0x34 209 #define TIMER_HP_T24_32BEGIN1 0x38 210 #define TIMER_HP_T32_24END0 0x3c 211 #define TIMER_HP_T32_24END1 0x40 212 #define TIMER_HP_BEGIN_END_VALID 0x44 213 #define TIMER_HP_SYNC_REQ 0x48 214 #define TIMER_HP_INTR_STATUS 0x4c 215 #define TIMER_HP_UPD_EN 0x50 216 217 /* GPIO */ 218 #define GPIO_SWPORT_DR_L 0x0000 219 #define GPIO_SWPORT_DR_H 0x0004 220 #define GPIO_SWPORT_DDR_L 0x0008 221 #define GPIO_SWPORT_DDR_H 0x000c 222 #define GPIO_INT_EN_L 0x0010 223 #define GPIO_INT_EN_H 0x0014 224 #define GPIO_INT_MASK_L 0x0018 225 #define GPIO_INT_MASK_H 0x001c 226 #define GPIO_INT_TYPE_L 0x0020 227 #define GPIO_INT_TYPE_H 0x0024 228 #define GPIO_INT_POLARITY_L 0x0028 229 #define GPIO_INT_POLARITY_H 0x002c 230 #define GPIO_INT_BOTHEDGE_L 0x0030 231 #define GPIO_INT_BOTHEDGE_H 0x0034 232 #define GPIO_DEBOUNCE_L 0x0038 233 #define GPIO_DEBOUNCE_H 0x003c 234 #define GPIO_DBCLK_DIV_EN_L 0x0040 235 #define GPIO_DBCLK_DIV_EN_H 0x0044 236 #define GPIO_DBCLK_DIV_CON 0x0048 237 #define GPIO_INT_STATUS 0x0050 238 #define GPIO_INT_RAWSTATUS 0x0058 239 #define GPIO_PORT_EOI_L 0x0060 240 #define GPIO_PORT_EOI_H 0x0064 241 #define GPIO_EXT_PORT 0x0070 242 #define GPIO_VER_ID 0x0078 243 #define GPIO_STORE_ST_L 0x0080 244 #define GPIO_STORE_ST_H 0x0084 245 #define GPIO_REG_GROUP_L 0x0100 246 #define GPIO_REG_GROUP_H 0x0104 247 #define GPIO_VIRTUAL_EN 0x0108 248 #define GPIO_REG_GROUP1_L 0x0110 249 #define GPIO_REG_GROUP1_H 0x0114 250 #define GPIO_REG_GROUP2_L 0x0118 251 #define GPIO_REG_GROUP2_H 0x011c 252 #define GPIO_REG_GROUP3_L 0x0120 253 #define GPIO_REG_GROUP3_H 0x0124 254 255 /* PWM */ 256 #define PMW_PWRCAPTURE_VAL 0x15c 257 258 #define SOC_RK3576A1 0x35760101 259 #define SOC_RK3576J1 0x35760a01 260 #define SOC_RK3576M1 0x35760d01 261 #define SOC_RK3576S1 0x35761301 262 #define SOC_UNKNOWN 0xeeee 263 #define SOC_ROOT 0x0 264 265 int rk_soc_is_(uint32_t soc_id); 266 uint32_t timer_hp_get_freq(void); 267 int soc_bus_div_sip_handler(uint32_t id, uint32_t cfg, uint32_t enable_msk); 268 void autocs_suspend(void); 269 void autocs_resume(void); 270 271 #endif /* __SOC_H__ */ 272