1*036935a8SXiaoDong Huang // SPDX-License-Identifier: BSD-3-Clause 2*036935a8SXiaoDong Huang /* 3*036935a8SXiaoDong Huang * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4*036935a8SXiaoDong Huang */ 5*036935a8SXiaoDong Huang 6*036935a8SXiaoDong Huang #include <assert.h> 7*036935a8SXiaoDong Huang #include <lib/mmio.h> 8*036935a8SXiaoDong Huang 9*036935a8SXiaoDong Huang #include <platform_def.h> 10*036935a8SXiaoDong Huang 11*036935a8SXiaoDong Huang #include <secure.h> 12*036935a8SXiaoDong Huang #include <soc.h> 13*036935a8SXiaoDong Huang 14*036935a8SXiaoDong Huang static void secure_timer_init(void) 15*036935a8SXiaoDong Huang { 16*036935a8SXiaoDong Huang /* gpu's cntvalue comes from stimer1 channel_5 */ 17*036935a8SXiaoDong Huang mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 18*036935a8SXiaoDong Huang TIMER_DIS); 19*036935a8SXiaoDong Huang 20*036935a8SXiaoDong Huang mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT0, 0xffffffff); 21*036935a8SXiaoDong Huang mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_LOAD_COUNT1, 0xffffffff); 22*036935a8SXiaoDong Huang 23*036935a8SXiaoDong Huang /* auto reload & enable the timer */ 24*036935a8SXiaoDong Huang mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, 25*036935a8SXiaoDong Huang TIMER_EN | TIMER_FMODE); 26*036935a8SXiaoDong Huang } 27*036935a8SXiaoDong Huang 28*036935a8SXiaoDong Huang void secure_init(void) 29*036935a8SXiaoDong Huang { 30*036935a8SXiaoDong Huang secure_timer_init(); 31*036935a8SXiaoDong Huang fw_init(); 32*036935a8SXiaoDong Huang 33*036935a8SXiaoDong Huang /* crypto secure controlled by crypto */ 34*036935a8SXiaoDong Huang mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), BITS_WITH_WMASK(0, 0x1, 4)); 35*036935a8SXiaoDong Huang mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), BITS_WITH_WMASK(0, 0x1, 5)); 36*036935a8SXiaoDong Huang 37*036935a8SXiaoDong Huang /* disable DP encryption mode */ 38*036935a8SXiaoDong Huang mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(1), BITS_WITH_WMASK(1, 0x1, 14)); 39*036935a8SXiaoDong Huang } 40