1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4 */ 5 6 #include <assert.h> 7 #include <errno.h> 8 9 #include <arch_helpers.h> 10 #include <bl31/bl31.h> 11 #include <common/debug.h> 12 #include <drivers/console.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <plat/common/platform.h> 16 #include <platform_def.h> 17 #include <pmu.h> 18 19 #include <cpus_on_fixed_addr.h> 20 #include <dmc_rk3576.h> 21 #include <plat_pm_helpers.h> 22 #include <plat_private.h> 23 #include <pm_pd_regs.h> 24 #include <secure.h> 25 #include <soc.h> 26 27 static struct psram_data_t *psram_sleep_cfg = 28 (struct psram_data_t *)&sys_sleep_flag_sram; 29 30 struct rk3576_sleep_ddr_data { 31 uint32_t cru_mode_con, secure_cru_mode; 32 uint32_t gpio0a_iomux_l, gpio0a_iomux_h, gpio0b_iomux_l; 33 uint32_t pmu2_bisr_glb_con; 34 uint32_t pmu2_c0_ack_sel_con0, pmu2_c1_ack_sel_con0, pmu2_c2_ack_sel_con0; 35 uint32_t pmu2_fast_pwr_con, pmu2_pwrgt_sft_con0; 36 uint32_t pmu0grf_soc_con0, pmu0grf_soc_con1, pmu0grf_soc_con5; 37 uint32_t pmu_pd_st, bus_idle_st; 38 uint32_t sys_sgrf_soc_con0; 39 uint32_t ddrgrf_cha_con2, ddrgrf_chb_con2; 40 }; 41 42 static struct rk3576_sleep_ddr_data ddr_data; 43 44 void rockchip_plat_mmu_el3(void) 45 { 46 #if PLAT_EXTRA_LD_SCRIPT 47 size_t sram_size; 48 49 sram_size = (char *)&__bl31_pmusram_text_end - 50 (char *)PMUSRAM_BASE; 51 mmap_add_region(PMUSRAM_BASE, PMUSRAM_BASE, 52 sram_size, MT_MEMORY | MT_RO | MT_SECURE); 53 54 sram_size = (char *)&__bl31_pmusram_data_end - 55 (char *)&__bl31_pmusram_data_start; 56 mmap_add_region((unsigned long)&__bl31_pmusram_data_start, 57 (unsigned long)&__bl31_pmusram_data_start, 58 sram_size, MT_DEVICE | MT_RW | MT_SECURE); 59 #endif 60 } 61 62 static int check_cpu_wfie(uint32_t cpu) 63 { 64 uint32_t loop = 0; 65 66 while ((mmio_read_32(SYS_GRF_BASE + SYSGRF_STATUS0) & BIT(cpu + 12)) == 0 && 67 (mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST) & BIT(cpu)) == 0 && 68 (loop < WFEI_CHECK_LOOP)) { 69 udelay(1); 70 loop++; 71 } 72 73 if (loop >= WFEI_CHECK_LOOP) { 74 WARN("%s: error, cpu%d (0x%x 0x%x)!\n", __func__, cpu, 75 mmio_read_32(SYS_GRF_BASE + SYSGRF_STATUS0), 76 mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST)); 77 return -EINVAL; 78 } 79 80 return 0; 81 } 82 83 static inline uint32_t cpu_power_domain_st(uint32_t cpu) 84 { 85 return !!(mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST) & 86 BIT(cpu + 16)); 87 } 88 89 static int cpu_power_domain_ctr(uint32_t cpu, uint32_t pd_state) 90 { 91 uint32_t loop = 0; 92 int ret = 0; 93 94 mmio_write_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu), 95 BITS_WITH_WMASK(pd_state, 0x1, 0)); 96 97 dsb(); 98 while ((cpu_power_domain_st(cpu) != pd_state) && (loop < PD_CTR_LOOP)) { 99 udelay(1); 100 loop++; 101 } 102 103 if (cpu_power_domain_st(cpu) != pd_state) { 104 WARN("%s: %d, %d, error!\n", __func__, cpu, pd_state); 105 ret = -EINVAL; 106 } 107 108 return ret; 109 } 110 111 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) 112 { 113 uint32_t val; 114 115 if ((mmio_read_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu_id)) & BIT(0)) != 0) 116 return core_pwr_pd; 117 118 val = mmio_read_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id)); 119 if ((val & BIT(pmu_cpu_pm_en)) != 0) { 120 if ((val & BIT(core_pwr_wfi_int)) != 0) 121 return core_pwr_wfi_int; 122 else if ((val & BIT(pmu_cpu_pm_sft_wakeup_en)) != 0) 123 return core_pwr_wfi_reset; 124 else 125 return core_pwr_wfi; 126 } else { 127 return -1; 128 } 129 } 130 131 static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value) 132 { 133 } 134 135 static int cpus_power_domain_on(uint32_t cpu_id) 136 { 137 uint32_t cfg_info; 138 /* 139 * There are two ways to powering on or off on core. 140 * 1) Control it power domain into on or off in PMU_PWRDN_CON reg 141 * 2) Enable the core power manage in PMU_CORE_PM_CON reg, 142 * then, if the core enter into wfi, it power domain will be 143 * powered off automatically. 144 */ 145 146 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id); 147 148 if (cfg_info == core_pwr_pd) { 149 /* disable core_pm cfg */ 150 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 151 BITS_WITH_WMASK(0, 0xf, 0)); 152 /* if the cores have be on, power off it firstly */ 153 if (cpu_power_domain_st(cpu_id) == pmu_pd_on) 154 cpu_power_domain_ctr(cpu_id, pmu_pd_off); 155 156 cpu_power_domain_ctr(cpu_id, pmu_pd_on); 157 } else { 158 if (cpu_power_domain_st(cpu_id) == pmu_pd_on) { 159 WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id); 160 return -EINVAL; 161 } 162 163 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 164 BITS_WITH_WMASK(1, 0x1, pmu_cpu_pm_sft_wakeup_en)); 165 dsb(); 166 } 167 168 return 0; 169 } 170 171 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) 172 { 173 uint32_t core_pm_value; 174 175 if (cpu_power_domain_st(cpu_id) == pmu_pd_off) 176 return 0; 177 178 if (pd_cfg == core_pwr_pd) { 179 if (check_cpu_wfie(cpu_id)) 180 return -EINVAL; 181 182 /* disable core_pm cfg */ 183 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 184 BITS_WITH_WMASK(0, 0xf, 0)); 185 186 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); 187 cpu_power_domain_ctr(cpu_id, pmu_pd_off); 188 } else { 189 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); 190 191 core_pm_value = BIT(pmu_cpu_pm_en) | BIT(pmu_cpu_pm_dis_int); 192 if (pd_cfg == core_pwr_wfi_int) 193 core_pm_value |= BIT(pmu_cpu_pm_int_wakeup_en); 194 else if (pd_cfg == core_pwr_wfi_reset) 195 core_pm_value |= BIT(pmu_cpu_pm_sft_wakeup_en); 196 197 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 198 BITS_WITH_WMASK(core_pm_value, 0xf, 0)); 199 dsb(); 200 } 201 202 return 0; 203 } 204 205 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) 206 { 207 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 208 209 assert(cpu_id < PLATFORM_CORE_COUNT); 210 assert(cpuson_flags[cpu_id] == 0); 211 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; 212 cpuson_entry_point[cpu_id] = entrypoint; 213 dsb(); 214 215 cpus_power_domain_on(cpu_id); 216 217 return PSCI_E_SUCCESS; 218 } 219 220 int rockchip_soc_cores_pwr_dm_off(void) 221 { 222 uint32_t cpu_id = plat_my_core_pos(); 223 224 cpus_power_domain_off(cpu_id, core_pwr_wfi); 225 226 return PSCI_E_SUCCESS; 227 } 228 229 int rockchip_soc_cores_pwr_dm_on_finish(void) 230 { 231 uint32_t cpu_id = plat_my_core_pos(); 232 233 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 234 BITS_WITH_WMASK(0, 0xf, 0)); 235 236 return PSCI_E_SUCCESS; 237 } 238 239 int rockchip_soc_cores_pwr_dm_suspend(void) 240 { 241 uint32_t cpu_id = plat_my_core_pos(); 242 243 assert(cpu_id < PLATFORM_CORE_COUNT); 244 assert(cpuson_flags[cpu_id] == 0); 245 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; 246 cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); 247 dsb(); 248 249 cpus_power_domain_off(cpu_id, core_pwr_wfi_int); 250 251 return PSCI_E_SUCCESS; 252 } 253 254 int rockchip_soc_cores_pwr_dm_resume(void) 255 { 256 uint32_t cpu_id = plat_my_core_pos(); 257 258 /* Disable core_pm */ 259 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), 260 BITS_WITH_WMASK(0, 0xf, 0)); 261 262 return PSCI_E_SUCCESS; 263 } 264 265 void nonboot_cpus_off(void) 266 { 267 uint32_t boot_cpu, cpu; 268 269 boot_cpu = plat_my_core_pos(); 270 271 /* turn off noboot cpus */ 272 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { 273 if (cpu == boot_cpu) 274 continue; 275 276 cpus_power_domain_off(cpu, core_pwr_pd); 277 } 278 } 279 280 static __pmusramfunc void ddr_resume(void) 281 { 282 uint32_t key_upd_msk = 283 mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST) & BIT(pmu_pd_vop) ? 0x3 : 0x7; 284 285 /* hptimer is 24M here */ 286 write_cntfrq_el0(24000000); 287 288 /* release cpu1~cpu7 to make pmu1_fsm exit */ 289 mmio_write_32(CCI_GRF_BASE + CCIGRF_CON(4), 0xffffffff); 290 mmio_write_32(LITCORE_GRF_BASE + COREGRF_CPU_CON(1), 291 BITS_WITH_WMASK(0x77, 0xff, 4)); 292 293 /* wait pmu1 fsm over */ 294 while ((mmio_read_32(PMU_BASE + PMU1_PWR_FSM) & 0xf) != 0) 295 ; 296 297 /* SOC_CON19.vop/center/cci_ddr_hash_key_update_en */ 298 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), 0x00070000); 299 dsb(); 300 301 /* SOC_CON19.vop/center/cci_ddr_hash_key_update_en */ 302 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), 0x00070000 | key_upd_msk); 303 304 /* SOC_STATUS.center/cci_ddr_hash_key_shift_ready */ 305 while (((mmio_read_32(SYS_SGRF_BASE + SYSSGRF_SOC_STATUS) >> 12) & key_upd_msk) != key_upd_msk) 306 ; 307 308 /* CCI_BASE.ctrl_override_reg Attr:W1C addrmap strobe */ 309 mmio_setbits_32(CCI_BASE + 0x0, 0x1 << 29); 310 311 /* SOC_CON19.vop/center/cci_ddr_hash_key_auto_update_en */ 312 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), 0x00700070); 313 } 314 315 static uint32_t clk_save[CRU_CLKGATE_CON_CNT + PHP_CRU_CLKGATE_CON_CNT + 316 SECURE_CRU_CLKGATE_CON_CNT + SECURE_SCRU_CLKGATE_CON_CNT + 317 PMU1CRU_CLKGATE_CON_CNT + PMU1SCRU_CLKGATE_CON_CNT]; 318 319 void clk_gate_con_disable(void) 320 { 321 int i; 322 323 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) { 324 /* Don't open wdt0 clk (cru_gate16[7:8] */ 325 if (i == 16) { 326 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 327 0xfe7f0000); 328 } else { 329 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 330 0xffff0000); 331 } 332 } 333 334 for (i = 0; i < PHP_CRU_CLKGATE_CON_CNT; i++) 335 mmio_write_32(PHP_CRU_BASE + PHP_CRU_CLKGATE_CON(i), 0xffff0000); 336 337 for (i = 0; i < SECURE_CRU_CLKGATE_CON_CNT; i++) 338 mmio_write_32(SECURE_CRU_BASE + SECURE_CRU_CLKGATE_CON(i), 0xffff0000); 339 340 for (i = 0; i < SECURE_SCRU_CLKGATE_CON_CNT; i++) 341 mmio_write_32(SECURE_CRU_BASE + SECURE_SCRU_CLKGATE_CON(i), 0xffff0000); 342 343 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++) 344 mmio_write_32(PMU1_CRU_BASE + PMU1CRU_CLKGATE_CON(i), 0xffff0000); 345 346 for (i = 0; i < PMU1SCRU_CLKGATE_CON_CNT; i++) 347 mmio_write_32(PMU1_CRU_BASE + PMU1SCRU_CLKGATE_CON(i), 0xffff0000); 348 } 349 350 void clk_gate_con_save(void) 351 { 352 int i, j = 0; 353 354 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) 355 clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); 356 357 for (i = 0; i < PHP_CRU_CLKGATE_CON_CNT; i++, j++) 358 clk_save[j] = mmio_read_32(PHP_CRU_BASE + PHP_CRU_CLKGATE_CON(i)); 359 360 for (i = 0; i < SECURE_CRU_CLKGATE_CON_CNT; i++, j++) 361 clk_save[j] = mmio_read_32(SECURE_CRU_BASE + SECURE_CRU_CLKGATE_CON(i)); 362 363 for (i = 0; i < SECURE_SCRU_CLKGATE_CON_CNT; i++, j++) 364 clk_save[j] = mmio_read_32(SECURE_CRU_BASE + SECURE_SCRU_CLKGATE_CON(i)); 365 366 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) 367 clk_save[j] = mmio_read_32(PMU1_CRU_BASE + PMU1CRU_CLKGATE_CON(i)); 368 369 for (i = 0; i < PMU1SCRU_CLKGATE_CON_CNT; i++, j++) 370 clk_save[j] = mmio_read_32(PMU1_CRU_BASE + PMU1SCRU_CLKGATE_CON(i)); 371 } 372 373 void clk_gate_con_restore(void) 374 { 375 int i, j = 0; 376 377 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) 378 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 379 WITH_16BITS_WMSK(clk_save[j])); 380 381 for (i = 0; i < PHP_CRU_CLKGATE_CON_CNT; i++, j++) 382 mmio_write_32(PHP_CRU_BASE + PHP_CRU_CLKGATE_CON(i), 383 WITH_16BITS_WMSK(clk_save[j])); 384 385 for (i = 0; i < SECURE_CRU_CLKGATE_CON_CNT; i++, j++) 386 mmio_write_32(SECURE_CRU_BASE + SECURE_CRU_CLKGATE_CON(i), 387 WITH_16BITS_WMSK(clk_save[j])); 388 389 for (i = 0; i < SECURE_SCRU_CLKGATE_CON_CNT; i++, j++) 390 mmio_write_32(SECURE_CRU_BASE + SECURE_SCRU_CLKGATE_CON(i), 391 WITH_16BITS_WMSK(clk_save[j])); 392 393 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) 394 mmio_write_32(PMU1_CRU_BASE + PMU1CRU_CLKGATE_CON(i), 395 WITH_16BITS_WMSK(clk_save[j])); 396 397 for (i = 0; i < PMU1SCRU_CLKGATE_CON_CNT; i++, j++) 398 mmio_write_32(PMU1_CRU_BASE + PMU1SCRU_CLKGATE_CON(i), 399 WITH_16BITS_WMSK(clk_save[j])); 400 } 401 402 void pmu_bus_idle_req(uint32_t bus, uint32_t state) 403 { 404 uint32_t wait_cnt = 0; 405 406 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), 407 BITS_WITH_WMASK(state, 0x1, bus % 16)); 408 409 while (pmu_bus_idle_st(bus) != state || 410 pmu_bus_idle_ack(bus) != state) { 411 if (++wait_cnt > BUS_IDLE_LOOP) 412 break; 413 udelay(1); 414 } 415 416 if (wait_cnt > BUS_IDLE_LOOP) 417 WARN("%s: can't wait state %d for bus %d (0x%x)\n", 418 __func__, state, bus, 419 mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST)); 420 } 421 422 static inline uint32_t pmu_power_domain_st(uint32_t pd) 423 { 424 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST) & BIT(pd) ? 425 pmu_pd_off : 426 pmu_pd_on; 427 } 428 429 int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) 430 { 431 uint32_t loop = 0; 432 int ret = 0; 433 434 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), 435 BITS_WITH_WMASK(pd_state, 0x1, pd % 16)); 436 dsb(); 437 438 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { 439 udelay(1); 440 loop++; 441 } 442 443 if (pmu_power_domain_st(pd) != pd_state) { 444 WARN("%s: %d, %d, (0x%x) error!\n", __func__, pd, pd_state, 445 mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST)); 446 ret = -EINVAL; 447 } 448 449 return ret; 450 } 451 452 static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) 453 { 454 uint32_t state; 455 456 if (pmu_power_domain_st(pd_id) == pd_state) 457 goto out; 458 459 if (pd_state == pmu_pd_on) 460 pmu_power_domain_ctr(pd_id, pd_state); 461 462 state = (pd_state == pmu_pd_off) ? pmu_bus_idle : pmu_bus_active; 463 464 switch (pd_id) { 465 case pmu_pd_npu: 466 pmu_bus_idle_req(pmu_bus_id_npusys, state); 467 break; 468 case pmu_pd_secure: 469 pmu_bus_idle_req(pmu_bus_id_secure, state); 470 break; 471 case pmu_pd_nvm: 472 pmu_bus_idle_req(pmu_bus_id_nvm, state); 473 break; 474 case pmu_pd_sd_gmac: 475 pmu_bus_idle_req(pmu_bus_id_gmac, state); 476 break; 477 case pmu_pd_audio: 478 pmu_bus_idle_req(pmu_bus_id_audio, state); 479 break; 480 case pmu_pd_php: 481 pmu_bus_idle_req(pmu_bus_id_php, state); 482 break; 483 case pmu_pd_subphp: 484 break; 485 case pmu_pd_vop: 486 pmu_bus_idle_req(pmu_bus_id_vop, state); 487 break; 488 case pmu_pd_vop_smart: 489 break; 490 case pmu_pd_vop_clst: 491 break; 492 case pmu_pd_vo1: 493 pmu_bus_idle_req(pmu_bus_id_vo1, state); 494 break; 495 case pmu_pd_vo0: 496 pmu_bus_idle_req(pmu_bus_id_vo0, state); 497 break; 498 case pmu_pd_usb: 499 pmu_bus_idle_req(pmu_bus_id_usb, state); 500 break; 501 case pmu_pd_vi: 502 pmu_bus_idle_req(pmu_bus_id_vi, state); 503 break; 504 case pmu_pd_vepu0: 505 pmu_bus_idle_req(pmu_bus_id_vepu0, state); 506 break; 507 case pmu_pd_vepu1: 508 pmu_bus_idle_req(pmu_bus_id_vepu1, state); 509 break; 510 case pmu_pd_vdec: 511 pmu_bus_idle_req(pmu_bus_id_vdec, state); 512 break; 513 case pmu_pd_vpu: 514 pmu_bus_idle_req(pmu_bus_id_vpu, state); 515 break; 516 case pmu_pd_nputop: 517 pmu_bus_idle_req(pmu_bus_id_nputop, state); 518 break; 519 case pmu_pd_npu0: 520 pmu_bus_idle_req(pmu_bus_id_npu0, state); 521 break; 522 case pmu_pd_npu1: 523 pmu_bus_idle_req(pmu_bus_id_npu1, state); 524 break; 525 case pmu_pd_gpu: 526 pmu_bus_idle_req(pmu_bus_id_gpu, state); 527 break; 528 default: 529 break; 530 } 531 532 if (pd_state == pmu_pd_off) 533 pmu_power_domain_ctr(pd_id, pd_state); 534 535 out: 536 return 0; 537 } 538 539 static void pmu_power_domains_suspend(void) 540 { 541 ddr_data.pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); 542 ddr_data.bus_idle_st = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST); 543 ddr_data.pmu2_pwrgt_sft_con0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(0)); 544 545 qos_save(); 546 547 pd_usb2phy_save(); 548 549 if ((ddr_data.pmu_pd_st & BIT(pmu_pd_php)) == 0) 550 pd_php_save(); 551 } 552 553 static void pmu_power_domains_resume(void) 554 { 555 int i; 556 557 for (i = 0; i < pmu_pd_id_max; i++) { 558 /* vop smart/clst pd is not controlled by pmu */ 559 if (i == pmu_pd_vop_smart || i == pmu_pd_vop_clst) 560 continue; 561 562 pmu_set_power_domain(i, !!(ddr_data.pmu_pd_st & BIT(i))); 563 } 564 565 /* restore vop smart/clst pd of pmu2_pwrgt_sft_con0 */ 566 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(0), 567 0x30000000 | ddr_data.pmu2_pwrgt_sft_con0); 568 569 for (i = pmu_bus_id_max - 1; i >= 0; i--) 570 pmu_bus_idle_req(i, !!(ddr_data.bus_idle_st & BIT(i))); 571 572 if ((ddr_data.pmu_pd_st & BIT(pmu_pd_php)) == 0) 573 pd_php_restore(); 574 575 pd_usb2phy_restore(); 576 577 qos_restore(); 578 } 579 580 static void ddr_sleep_config(void) 581 { 582 ddr_data.ddrgrf_cha_con2 = 583 mmio_read_32(DDR_GRF_BASE + DDRGRF_CHA_CON(2)); 584 ddr_data.ddrgrf_chb_con2 = 585 mmio_read_32(DDR_GRF_BASE + DDRGRF_CHB_CON(2)); 586 587 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHA_CON(2), 0x0a000a00); 588 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHB_CON(2), 0x0a000a00); 589 } 590 591 static void ddr_sleep_config_restore(void) 592 { 593 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHA_CON(2), 594 WITH_16BITS_WMSK(ddr_data.ddrgrf_cha_con2)); 595 mmio_write_32(DDR_GRF_BASE + DDRGRF_CHB_CON(2), 596 WITH_16BITS_WMSK(ddr_data.ddrgrf_chb_con2)); 597 } 598 599 static void sleep_pin_config(void) 600 { 601 /* pwr0 sleep: gpio0_a3 */ 602 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(1), 603 BITS_WITH_WMASK(0x7, 0xf, 0)); 604 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(0), 605 BITS_WITH_WMASK(0, 0x1, 7)); 606 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_L, 607 BITS_WITH_WMASK(9, 0xfu, 12)); 608 } 609 610 static void pmu_sleep_config(void) 611 { 612 uint32_t pmu1_wkup_int_con; 613 uint32_t pmu1_pwr_con, pmu1_ddr_pwr_con, pmu1cru_pwr_con, pmu1_pll_pd_con; 614 uint32_t pmu2_bus_idle_con[2], pmu2_pwr_gt_con[2]; 615 uint32_t key_upd_msk = ddr_data.pmu_pd_st & BIT(pmu_pd_vop) ? 0x3 : 0x7; 616 uint32_t fw_lkp_upd_msk = ddr_data.pmu_pd_st & BIT(pmu_pd_npu) ? 0x3 : 0x7; 617 uint32_t fw_ddr_upd_msk = key_upd_msk; 618 uint32_t pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); 619 uint32_t bus_idle_st = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST); 620 621 ddr_data.pmu2_bisr_glb_con = mmio_read_32(PMU_BASE + PMU2_BISR_GLB_CON); 622 623 ddr_data.pmu2_fast_pwr_con = 624 mmio_read_32(PMU_BASE + PMU2_FAST_POWER_CON); 625 626 ddr_data.pmu2_c0_ack_sel_con0 = 627 mmio_read_32(PMU_BASE + PMU2_C0_PWRACK_BYPASS_CON(0)); 628 ddr_data.pmu2_c1_ack_sel_con0 = 629 mmio_read_32(PMU_BASE + PMU2_C1_PWRACK_BYPASS_CON(0)); 630 ddr_data.pmu2_c2_ack_sel_con0 = 631 mmio_read_32(PMU_BASE + PMU2_C2_PWRACK_BYPASS_CON(0)); 632 ddr_data.pmu0grf_soc_con5 = 633 mmio_read_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(5)); 634 635 /* set tsadc_shut_m0 pin iomux to gpio */ 636 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_L, 637 BITS_WITH_WMASK(0, 0xf, 4)); 638 639 pmu1_wkup_int_con = 640 BIT(pmu_wkup_cpu0_int) | 641 BIT(pmu_wkup_gpio0_int); 642 643 pmu1_pwr_con = 644 BIT(pmu_powermode_en) | 645 /* BIT(pmu_scu0_byp) | */ 646 /* BIT(pmu_scu1_byp) | */ 647 /* BIT(pmu_cci_byp) | */ 648 /* BIT(pmu_bus_byp) | */ 649 /* BIT(pmu_ddr_byp) | */ 650 /* BIT(pmu_pwrgt_byp) | */ 651 /* BIT(pmu_cru_byp) | */ 652 BIT(pmu_qch_byp) | 653 /* BIT(pmu_wfi_byp) | */ 654 BIT(pmu_slp_cnt_en); 655 656 pmu1_ddr_pwr_con = 0; 657 658 pmu1_pll_pd_con = 659 BIT(pmu_bpll_pd_en) | 660 BIT(pmu_lpll_pd_en) | 661 BIT(pmu_spll_pd_en) | 662 BIT(pmu_gpll_pd_en) | 663 BIT(pmu_cpll_pd_en) | 664 BIT(pmu_ppll_pd_en) | 665 BIT(pmu_aupll_pd_en) | 666 BIT(pmu_vpll_pd_en); 667 668 pmu1cru_pwr_con = 669 BIT(pmu_alive_osc_mode_en) | 670 BIT(pmu_io_sleep_en) | 671 BIT(pmu_power_off_en); 672 673 pmu2_bus_idle_con[0] = 0xffff & ~(bus_idle_st & 0xffff); 674 pmu2_bus_idle_con[1] = 0x3fff & ~(bus_idle_st >> 16); 675 676 pmu2_pwr_gt_con[0] = 0xffff & ~(pmu_pd_st & 0xffff); 677 pmu2_pwr_gt_con[1] = 0x03ff & ~(pmu_pd_st >> 16); 678 679 pmu2_pwr_gt_con[0] &= 680 ~(BIT(pmu_pd_secure) | 681 BIT(pmu_pd_bus) | 682 BIT(pmu_pd_center) | 683 BIT(pmu_pd_ddr)); 684 685 mmio_write_32(PMU_BASE + PMU2_BUS_IDLEACK_BYPASS_CON, 0x00030003); 686 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON0, 0x03ff0000); 687 688 /* disable repair */ 689 mmio_write_32(PMU_BASE + PMU2_BISR_GLB_CON, 0x00010000); 690 691 /* disable ddr_hash_key update. 692 * enable disable ddr_hash_key auto update. 693 * wait ddr_hash_key auto update. 694 */ 695 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(19), 696 BITS_WITH_WMASK(key_upd_msk, 0x7, 8)); 697 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON1, 698 BITS_WITH_WMASK(fw_lkp_upd_msk, 0x7, 10)); 699 mmio_write_32(SYS_SGRF_FW_BASE + FW_SGRF_KEYUPD_CON1, 700 BITS_WITH_WMASK(fw_ddr_upd_msk, 0x7u, 13)); 701 702 mmio_write_32(PMU_BASE + PMU0_PMIC_STABLE_CNT_THRES, 24000 * 5); 703 mmio_write_32(PMU_BASE + PMU0_OSC_STABLE_CNT_THRES, 24000 * 5); 704 705 mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT_THRESH, 24000 * 5); 706 mmio_write_32(PMU_BASE + PMU1_STABLE_CNT_THRESH, 24000 * 5); 707 708 mmio_write_32(PMU_BASE + PMU1_SLEEP_CNT_THRESH, 24000 * 15); 709 710 /* Pmu's clk has switched to 24M back When pmu FSM counts 711 * the follow counters, so we should use 24M to calculate 712 * these counters. 713 */ 714 mmio_write_32(PMU_BASE + PMU0_WAKEUP_RST_CLR_CNT_THRES, 12000); 715 716 mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT_THRESH, 12000); 717 mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT_THRESH, 12000); 718 mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT_THRESH, 719 24000 * 2); 720 721 mmio_write_32(PMU_BASE + PMU2_SCU0_PWRUP_CNT_THRESH, 0); 722 mmio_write_32(PMU_BASE + PMU2_SCU0_PWRDN_CNT_THRESH, 0); 723 mmio_write_32(PMU_BASE + PMU2_SCU0_STABLE_CNT_THRESH, 0); 724 725 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_0, 0); 726 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_0, 0); 727 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_1, 0); 728 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_1, 0); 729 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_2, 0); 730 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_2, 0); 731 mmio_write_32(PMU_BASE + PMU2_FAST_POWER_CON, 0xffff0007); 732 733 /* pmu_clst_idle_con */ 734 mmio_write_32(PMU_BASE + PMU2_CLUSTER0_IDLE_CON, 0xffff0007); 735 mmio_write_32(PMU_BASE + PMU2_CLUSTER1_IDLE_CON, 0xffff0007); 736 737 /* pmu_scu_pwr_con */ 738 /* L2's flush and idle by hardware, so need to enable wfil2 bypass */ 739 mmio_write_32(PMU_BASE + PMU2_SCU0_PWR_CON, 0xffff020f); 740 mmio_write_32(PMU_BASE + PMU2_SCU1_PWR_CON, 0xffff020f); 741 mmio_write_32(PMU_BASE + PMU2_SCU0_AUTO_PWR_CON, 0x00070000); 742 mmio_write_32(PMU_BASE + PMU2_SCU1_AUTO_PWR_CON, 0x00070000); 743 744 mmio_write_32(PMU_BASE + PMU2_CCI_PWR_CON, 0xffff0009); 745 746 /* pmu_int_msk_con */ 747 /* mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, BITS_WITH_WMASK(1, 0x1, 0)); */ 748 749 /* pmu_pwr_con */ 750 mmio_write_32(PMU_BASE + PMU1_PWR_CON, WITH_16BITS_WMSK(pmu1_pwr_con)); 751 752 /* pmu_cru_pwr_conx */ 753 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), WITH_16BITS_WMSK(pmu1cru_pwr_con)); 754 755 /* pmu_ddr_pwr_con */ 756 mmio_write_32(PMU_BASE + PMU0_DDR_RET_CON(1), 0xffff0000); 757 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(0), WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); 758 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(1), WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); 759 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(0), 0x03ff03ff); 760 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(1), 0x03ff03ff); 761 762 /* pll_pd */ 763 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), WITH_16BITS_WMSK(pmu1_pll_pd_con)); 764 765 /* bus idle */ 766 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), WITH_16BITS_WMSK(pmu2_bus_idle_con[0])); 767 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), WITH_16BITS_WMSK(pmu2_bus_idle_con[1])); 768 769 /* power gate */ 770 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), WITH_16BITS_WMSK(pmu2_pwr_gt_con[0])); 771 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), WITH_16BITS_WMSK(pmu2_pwr_gt_con[1])); 772 773 /* vol gate */ 774 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), 0xffff0031); 775 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(1), 0xffff0200); 776 777 /* wakeup source */ 778 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); 779 780 /* ppll clamp */ 781 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(5), 0x00400040); 782 783 /* usbphy clamp */ 784 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(5), 785 BITS_WITH_WMASK(0x9, 0x9, 2)); 786 787 /* big core pwr ack bypass */ 788 mmio_write_32(PMU_BASE + PMU2_C0_PWRACK_BYPASS_CON(0), 0x01000100); 789 mmio_write_32(PMU_BASE + PMU2_C1_PWRACK_BYPASS_CON(0), 0x01000100); 790 mmio_write_32(PMU_BASE + PMU2_C2_PWRACK_BYPASS_CON(0), 0x01000100); 791 } 792 793 static void pmu_sleep_restore(void) 794 { 795 mmio_write_32(PMU_BASE + PMU0_INFO_TX_CON, 0xffff0000); 796 mmio_write_32(PMU_BASE + PMU2_DEBUG_INFO_SEL, 0xffff0000); 797 mmio_write_32(PMU_BASE + PMU2_CLUSTER0_IDLE_CON, 0xffff0000); 798 mmio_write_32(PMU_BASE + PMU2_SCU0_PWR_CON, 0xffff0000); 799 mmio_write_32(PMU_BASE + PMU2_CCI_PWR_CON, 0xffff0000); 800 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0xffff0000); 801 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); 802 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), 0xffff0000); 803 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(0), 0xffff0000); 804 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(1), 0xffff0000); 805 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(0), 0xffff0000); 806 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(1), 0xffff0000); 807 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), 0xffff0000); 808 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), 0xffff0000); 809 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), 0xffff0000); 810 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), 0xffff0000); 811 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), 0xffff0000); 812 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), 0xffff0000); 813 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(1), 0xffff0000); 814 mmio_write_32(PMU_BASE + PMU2_BUS_IDLEACK_BYPASS_CON, 0xffff0000); 815 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); 816 mmio_write_32(PMU_BASE + PMU2_FAST_POWER_CON, 817 WITH_16BITS_WMSK(ddr_data.pmu2_fast_pwr_con)); 818 mmio_write_32(PMU_BASE + PMU2_BISR_GLB_CON, 819 WITH_16BITS_WMSK(ddr_data.pmu2_bisr_glb_con)); 820 821 mmio_write_32(PMU_BASE + PMU2_C0_PWRACK_BYPASS_CON(0), 822 WITH_16BITS_WMSK(ddr_data.pmu2_c0_ack_sel_con0)); 823 mmio_write_32(PMU_BASE + PMU2_C1_PWRACK_BYPASS_CON(0), 824 WITH_16BITS_WMSK(ddr_data.pmu2_c1_ack_sel_con0)); 825 mmio_write_32(PMU_BASE + PMU2_C2_PWRACK_BYPASS_CON(0), 826 WITH_16BITS_WMSK(ddr_data.pmu2_c2_ack_sel_con0)); 827 828 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(5), 829 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con5)); 830 } 831 832 static void secure_watchdog_disable(void) 833 { 834 ddr_data.sys_sgrf_soc_con0 = 835 mmio_read_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0)); 836 837 /* pause wdt_s */ 838 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), 839 BITS_WITH_WMASK(1, 0x1, 14)); 840 } 841 842 static void secure_watchdog_restore(void) 843 { 844 mmio_write_32(SYS_SGRF_BASE + SYSSGRF_SOC_CON(0), 845 ddr_data.sys_sgrf_soc_con0 | 846 BITS_WMSK(0x1, 14)); 847 848 if (mmio_read_32(WDT_S_BASE + WDT_CR) & WDT_EN) 849 mmio_write_32(WDT_S_BASE + WDT_CRR, 0x76); 850 } 851 852 static void soc_sleep_config(void) 853 { 854 ddr_data.pmu0grf_soc_con0 = 855 mmio_read_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(0)); 856 ddr_data.pmu0grf_soc_con1 = 857 mmio_read_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(1)); 858 859 ddr_data.gpio0a_iomux_l = 860 mmio_read_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_L); 861 ddr_data.gpio0a_iomux_h = 862 mmio_read_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_H); 863 ddr_data.gpio0b_iomux_l = 864 mmio_read_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0B_IOMUX_SEL_L); 865 866 sleep_pin_config(); 867 pmu_sleep_config(); 868 ddr_sleep_config(); 869 secure_watchdog_disable(); 870 } 871 872 static void soc_sleep_restore(void) 873 { 874 secure_watchdog_restore(); 875 ddr_sleep_config_restore(); 876 pmu_sleep_restore(); 877 878 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_L, 879 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_l)); 880 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0A_IOMUX_SEL_H, 881 WITH_16BITS_WMSK(ddr_data.gpio0a_iomux_h)); 882 mmio_write_32(PMU0_IOC_BASE + PMUIO0_IOC_GPIO0B_IOMUX_SEL_L, 883 WITH_16BITS_WMSK(ddr_data.gpio0b_iomux_l)); 884 885 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(1), 886 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con1)); 887 mmio_write_32(PMU0_GRF_BASE + PMU0GRF_SOC_CON(0), 888 WITH_16BITS_WMSK(ddr_data.pmu0grf_soc_con0)); 889 } 890 891 static void pm_pll_suspend(void) 892 { 893 ddr_data.cru_mode_con = mmio_read_32(CRU_BASE + 0x280); 894 ddr_data.secure_cru_mode = mmio_read_32(SECURE_CRU_BASE + 0x4280); 895 896 /* bpll gpll vpll aupll cpll spll switch to slow mode */ 897 mmio_write_32(CRU_BASE + 0x280, 0x03ff0000); 898 mmio_write_32(SECURE_CRU_BASE + 0x4280, 0x00030000); 899 900 /* hclk_pmu_cm0_root_i_sel to 24M */ 901 mmio_write_32(PMU1_CRU_BASE + PMU1CRU_CLKSEL_CON(4), 902 BITS_WITH_WMASK(0x3, 0x3, 2)); 903 } 904 905 static void pm_pll_restore(void) 906 { 907 mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); 908 mmio_write_32(SECURE_CRU_BASE + 0x4280, 909 WITH_16BITS_WMSK(ddr_data.secure_cru_mode)); 910 } 911 912 int rockchip_soc_sys_pwr_dm_suspend(void) 913 { 914 psram_sleep_cfg->pm_flag &= ~PM_WARM_BOOT_BIT; 915 916 clk_gate_con_save(); 917 clk_gate_con_disable(); 918 dmc_save(); 919 pmu_power_domains_suspend(); 920 soc_sleep_config(); 921 pm_pll_suspend(); 922 pd_core_save(); 923 924 return 0; 925 } 926 927 int rockchip_soc_sys_pwr_dm_resume(void) 928 { 929 pd_core_restore(); 930 pm_pll_restore(); 931 soc_sleep_restore(); 932 pmu_power_domains_resume(); 933 plat_rockchip_gic_cpuif_enable(); 934 dmc_restore(); 935 clk_gate_con_restore(); 936 937 psram_sleep_cfg->pm_flag |= PM_WARM_BOOT_BIT; 938 939 return 0; 940 } 941 942 static int rockchip_reboot_is_rbrom(void) 943 { 944 return mmio_read_32(PMU0_GRF_BASE + PMU0GRF_OS_REG(16)) == 945 BOOT_BROM_DOWNLOAD; 946 } 947 948 static void rockchip_soc_soft_reset_check_rstout(void) 949 { 950 /* 951 * Maskrom enter maskrom-usb mode according to os_reg0 which 952 * will be reset by NPOR. So disable tsadc_shut_m0 if we want 953 * to maskrom-usb mode. 954 */ 955 if (rockchip_reboot_is_rbrom() != 0) { 956 /* write BOOT_BROM_DOWNLOAD to os_reg0 */ 957 mmio_write_32(PMU1_GRF_BASE + PMU1GRF_OS_REG(0), BOOT_BROM_DOWNLOAD); 958 959 /* disable first/tsadc/wdt reset output */ 960 mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(0), 0x00070000); 961 962 /* clear reset hold */ 963 mmio_write_32(PMU0SGRF_BASE + PMU0SGRF_SOC_CON(1), 0xffff0000); 964 mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(16), 0xffff0000); 965 mmio_write_32(PMU1SGRF_BASE + PMU1SGRF_SOC_CON(17), 0xffff0000); 966 } 967 } 968 969 void __dead2 rockchip_soc_soft_reset(void) 970 { 971 rockchip_soc_soft_reset_check_rstout(); 972 973 /* pll slow mode */ 974 mmio_write_32(CRU_BASE + CRU_MODE_CON, 0x003f0000); 975 976 dsb(); 977 isb(); 978 979 INFO("system reset......\n"); 980 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); 981 982 /* 983 * Maybe the HW needs some times to reset the system, 984 * so we do not hope the core to execute valid codes. 985 */ 986 while (1) { 987 wfi(); 988 } 989 } 990 991 void __dead2 rockchip_soc_system_off(void) 992 { 993 INFO("system poweroff......\n"); 994 995 /* gpio0_a3 config output */ 996 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DDR_L, 997 BITS_WITH_WMASK(1, 0x1, 3)); 998 999 /* gpio0_a3 config output high level */ 1000 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DR_L, 1001 BITS_WITH_WMASK(1, 0x1, 3)); 1002 dsb(); 1003 1004 /* 1005 * Maybe the HW needs some times to reset the system, 1006 * so we do not hope the core to execute valid codes. 1007 */ 1008 while (1) { 1009 wfi(); 1010 } 1011 } 1012 1013 static void rockchip_pmu_pd_repair_init(void) 1014 { 1015 INFO("enable memory repair\n"); 1016 /* Enable gpu and npu repair */ 1017 mmio_write_32(PMU_BASE + PMU2_BISR_PDGEN_CON(1), 1018 BITS_WITH_WMASK(0xf, 0xf, 6)); 1019 } 1020 1021 void plat_rockchip_pmu_init(void) 1022 { 1023 int cpu; 1024 1025 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) 1026 cpuson_flags[cpu] = 0; 1027 1028 psram_sleep_cfg->sp = PSRAM_SP_TOP; 1029 psram_sleep_cfg->ddr_func = (uint64_t)ddr_resume; 1030 psram_sleep_cfg->ddr_data = 0; 1031 psram_sleep_cfg->ddr_flag = 0; 1032 psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; 1033 psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT; 1034 1035 nonboot_cpus_off(); 1036 1037 /* 1038 * When perform idle operation, corresponding clock can be 1039 * opened or gated automatically. 1040 */ 1041 mmio_write_32(PMU_BASE + PMU2_NOC_AUTO_CON(0), 0xffffffff); 1042 mmio_write_32(PMU_BASE + PMU2_NOC_AUTO_CON(1), 0xffffffff); 1043 1044 /* remap pmusram to 0x00000000 */ 1045 mmio_write_32(PMU0SGRF_BASE + PMU0SGRF_SOC_CON(2), BITS_WITH_WMASK(1, 0x3, 0)); 1046 1047 /* enable power off VD_NPU by hrdware */ 1048 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), 1049 BITS_WITH_WMASK(0x1, 0x1, 0)); 1050 1051 rockchip_pmu_pd_repair_init(); 1052 1053 pm_reg_rgns_init(); 1054 } 1055