1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2025, Rockchip Electronics Co., Ltd. 4 */ 5 6 #include <assert.h> 7 #include <errno.h> 8 9 #include <arch_helpers.h> 10 #include <bl31/bl31.h> 11 #include <common/debug.h> 12 #include <drivers/console.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <pmu.h> 18 19 #include <plat_pm_helpers.h> 20 #include <plat_private.h> 21 #include <pm_pd_regs.h> 22 #include <rk3576_clk.h> 23 #include <soc.h> 24 25 #define WMSK_VAL 0xffff0000 26 27 static struct reg_region qos_reg_rgns[] = { 28 [qos_decom] = REG_REGION(0x08, 0x18, 4, 0x27f00000, 0), 29 [qos_dmac0] = REG_REGION(0x08, 0x18, 4, 0x27f00080, 0), 30 [qos_dmac1] = REG_REGION(0x08, 0x18, 4, 0x27f00100, 0), 31 [qos_dmac2] = REG_REGION(0x08, 0x18, 4, 0x27f00180, 0), 32 [qos_bus_mcu] = REG_REGION(0x08, 0x18, 4, 0x27f00200, 0), 33 [qos_can0] = REG_REGION(0x08, 0x18, 4, 0x27f00280, 0), 34 [qos_can1] = REG_REGION(0x08, 0x18, 4, 0x27f00300, 0), 35 [qos_cci_m0] = REG_REGION(0x08, 0x18, 4, 0x27f01000, 0), 36 [qos_cci_m1] = REG_REGION(0x08, 0x18, 4, 0x27f18880, 0), 37 [qos_cci_m2] = REG_REGION(0x08, 0x18, 4, 0x27f18900, 0), 38 [qos_dap_lite] = REG_REGION(0x08, 0x18, 4, 0x27f01080, 0), 39 [qos_hdcp1] = REG_REGION(0x08, 0x18, 4, 0x27f02000, 0), 40 [qos_ddr_mcu] = REG_REGION(0x08, 0x18, 4, 0x27f03000, 0), 41 [qos_fspi1] = REG_REGION(0x08, 0x18, 4, 0x27f04000, 0), 42 [qos_gmac0] = REG_REGION(0x08, 0x18, 4, 0x27f04080, 0), 43 [qos_gmac1] = REG_REGION(0x08, 0x18, 4, 0x27f04100, 0), 44 [qos_sdio] = REG_REGION(0x08, 0x18, 4, 0x27f04180, 0), 45 [qos_sdmmc] = REG_REGION(0x08, 0x18, 4, 0x27f04200, 0), 46 [qos_flexbus] = REG_REGION(0x08, 0x18, 4, 0x27f04280, 0), 47 [qos_gpu] = REG_REGION(0x08, 0x18, 4, 0x27f05000, 0), 48 [qos_vepu1] = REG_REGION(0x08, 0x18, 4, 0x27f06000, 0), 49 [qos_npu_mcu] = REG_REGION(0x08, 0x18, 4, 0x27f08000, 0), 50 [qos_npu_nsp0] = REG_REGION(0x08, 0x18, 4, 0x27f08080, 0), 51 [qos_npu_nsp1] = REG_REGION(0x08, 0x18, 4, 0x27f08100, 0), 52 [qos_npu_m0] = REG_REGION(0x08, 0x18, 4, 0x27f20000, 0), 53 [qos_npu_m1] = REG_REGION(0x08, 0x18, 4, 0x27f21000, 0), 54 [qos_npu_m0ro] = REG_REGION(0x08, 0x18, 4, 0x27f22080, 0), 55 [qos_npu_m1ro] = REG_REGION(0x08, 0x18, 4, 0x27f22100, 0), 56 [qos_emmc] = REG_REGION(0x08, 0x18, 4, 0x27f09000, 0), 57 [qos_fspi0] = REG_REGION(0x08, 0x18, 4, 0x27f09080, 0), 58 [qos_mmu0] = REG_REGION(0x08, 0x18, 4, 0x27f0a000, 0), 59 [qos_mmu1] = REG_REGION(0x08, 0x18, 4, 0x27f0a080, 0), 60 [qos_pmu_mcu] = REG_REGION(0x08, 0x18, 4, 0x27f0b000, 0), 61 [qos_rkvdec] = REG_REGION(0x08, 0x18, 4, 0x27f0c000, 0), 62 [qos_crypto] = REG_REGION(0x08, 0x18, 4, 0x27f0d000, 0), 63 [qos_mmu2] = REG_REGION(0x08, 0x18, 4, 0x27f0e000, 0), 64 [qos_ufshc] = REG_REGION(0x08, 0x18, 4, 0x27f0e080, 0), 65 [qos_vepu0] = REG_REGION(0x08, 0x18, 4, 0x27f0f000, 0), 66 [qos_isp_mro] = REG_REGION(0x08, 0x18, 4, 0x27f10000, 0), 67 [qos_isp_mwo] = REG_REGION(0x08, 0x18, 4, 0x27f10080, 0), 68 [qos_vicap_m0] = REG_REGION(0x08, 0x18, 4, 0x27f10100, 0), 69 [qos_vpss_mro] = REG_REGION(0x08, 0x18, 4, 0x27f10180, 0), 70 [qos_vpss_mwo] = REG_REGION(0x08, 0x18, 4, 0x27f10200, 0), 71 [qos_hdcp0] = REG_REGION(0x08, 0x18, 4, 0x27f11000, 0), 72 [qos_vop_m0] = REG_REGION(0x08, 0x18, 4, 0x27f12800, 0), 73 [qos_vop_m1ro] = REG_REGION(0x08, 0x18, 4, 0x27f12880, 0), 74 [qos_ebc] = REG_REGION(0x08, 0x18, 4, 0x27f13000, 0), 75 [qos_rga0] = REG_REGION(0x08, 0x18, 4, 0x27f13080, 0), 76 [qos_rga1] = REG_REGION(0x08, 0x18, 4, 0x27f13100, 0), 77 [qos_jpeg] = REG_REGION(0x08, 0x18, 4, 0x27f13180, 0), 78 [qos_vdpp] = REG_REGION(0x08, 0x18, 4, 0x27f13200, 0), 79 [qos_dma2ddr] = REG_REGION(0x08, 0x18, 4, 0x27f15880, 0), 80 }; 81 82 static struct reg_region pd_bcore_reg_rgns[] = { 83 /* bcore cru */ 84 /* REG_REGION(0x280, 0x280, 4, BIGCORE0CRU_BASE, WMSK_VAL), */ 85 REG_REGION(0x300, 0x30c, 4, BIGCORE_CRU_BASE, WMSK_VAL), 86 REG_REGION(0x800, 0x804, 4, BIGCORE_CRU_BASE, WMSK_VAL), 87 REG_REGION(0xa00, 0xa0c, 4, BIGCORE_CRU_BASE, WMSK_VAL), 88 REG_REGION(0xcc0, 0xcc0, 4, BIGCORE_CRU_BASE, 0), 89 REG_REGION(0xf28, 0xf28, 8, BIGCORE_CRU_BASE, 0), 90 REG_REGION(0xf2c, 0xf2c, 8, BIGCORE_CRU_BASE, WMSK_VAL), 91 92 /* bcore_grf */ 93 REG_REGION(0x34, 0x3c, 4, BIGCORE_GRF_BASE, WMSK_VAL), 94 REG_REGION(0x44, 0x44, 4, BIGCORE_GRF_BASE, WMSK_VAL), 95 }; 96 97 static struct reg_region pd_core_reg_rgns[] = { 98 /* cci cru */ 99 REG_REGION(0x310, 0x310, 4, CCI_CRU_BASE, WMSK_VAL), 100 REG_REGION(0x804, 0x808, 4, CCI_CRU_BASE, WMSK_VAL), 101 REG_REGION(0xa04, 0xa08, 4, CCI_CRU_BASE, WMSK_VAL), 102 REG_REGION(0xc50, 0xc58, 4, CCI_CRU_BASE, WMSK_VAL), 103 REG_REGION(0xd00, 0xd00, 8, CCI_CRU_BASE, 0), 104 REG_REGION(0xd04, 0xd04, 8, CCI_CRU_BASE, WMSK_VAL), 105 /* Restore lpll registers after clksel_* registers. Because lpll 106 * may be turned off during restoring, which cause cci_cru to lost clock. 107 */ 108 REG_REGION(0x040, 0x044, 4, CCI_CRU_BASE, WMSK_VAL), 109 REG_REGION(0x048, 0x048, 4, CCI_CRU_BASE, 0), 110 REG_REGION(0x04c, 0x058, 4, CCI_CRU_BASE, WMSK_VAL), 111 112 /* lcore cru */ 113 /* REG_REGION(0x280, 0x280, 4, BIGCORE1CRU_BASE, WMSK_VAL), */ 114 REG_REGION(0x300, 0x30c, 4, LITTLE_CRU_BASE, WMSK_VAL), 115 REG_REGION(0x800, 0x804, 4, LITTLE_CRU_BASE, WMSK_VAL), 116 REG_REGION(0xa00, 0xa0c, 4, LITTLE_CRU_BASE, WMSK_VAL), 117 REG_REGION(0xcc0, 0xcc0, 4, LITTLE_CRU_BASE, 0), 118 REG_REGION(0xf38, 0xf38, 8, LITTLE_CRU_BASE, 0), 119 REG_REGION(0xf3c, 0xf3c, 8, LITTLE_CRU_BASE, WMSK_VAL), 120 121 /* bcore cru */ 122 /* REG_REGION(0x280, 0x280, 4, BIGCORE0CRU_BASE, WMSK_VAL), */ 123 REG_REGION(0x300, 0x30c, 4, BIGCORE_CRU_BASE, WMSK_VAL), 124 REG_REGION(0x800, 0x804, 4, BIGCORE_CRU_BASE, WMSK_VAL), 125 REG_REGION(0xa00, 0xa0c, 4, BIGCORE_CRU_BASE, WMSK_VAL), 126 REG_REGION(0xcc0, 0xcc0, 4, BIGCORE_CRU_BASE, 0), 127 REG_REGION(0xf28, 0xf28, 8, BIGCORE_CRU_BASE, 0), 128 REG_REGION(0xf2c, 0xf2c, 8, BIGCORE_CRU_BASE, WMSK_VAL), 129 130 /* cci grf */ 131 REG_REGION(0x00, 0x10, 4, CCI_GRF_BASE, WMSK_VAL), 132 REG_REGION(0x54, 0x54, 4, CCI_GRF_BASE, WMSK_VAL), 133 134 /* lcore_grf */ 135 REG_REGION(0x34, 0x3c, 4, LITCORE_GRF_BASE, WMSK_VAL), 136 REG_REGION(0x44, 0x44, 4, LITCORE_GRF_BASE, WMSK_VAL), 137 138 /* bcore_grf */ 139 REG_REGION(0x34, 0x3c, 4, BIGCORE_GRF_BASE, WMSK_VAL), 140 REG_REGION(0x44, 0x44, 4, BIGCORE_GRF_BASE, WMSK_VAL), 141 }; 142 143 static struct reg_region pd_php_reg_rgns[] = { 144 /* php_grf */ 145 REG_REGION(0x004, 0x00c, 4, PHP_GRF_BASE, WMSK_VAL), 146 REG_REGION(0x010, 0x018, 4, PHP_GRF_BASE, 0), 147 REG_REGION(0x01c, 0x020, 4, PHP_GRF_BASE, WMSK_VAL), 148 REG_REGION(0x048, 0x048, 4, PHP_GRF_BASE, 0), 149 }; 150 151 static struct reg_region pd_usb2phy_reg_rgns[] = { 152 /* usb */ 153 REG_REGION(0x00, 0x14, 4, USB2PHY0_GRF_BASE, WMSK_VAL), 154 REG_REGION(0x40, 0x40, 4, USB2PHY0_GRF_BASE, WMSK_VAL), 155 REG_REGION(0x44, 0x50, 4, USB2PHY0_GRF_BASE, 0), 156 REG_REGION(0x00, 0x14, 4, USB2PHY1_GRF_BASE, WMSK_VAL), 157 REG_REGION(0x08, 0x08, 4, USBDPPHY_GRF_BASE, WMSK_VAL), 158 }; 159 160 #define PLL_LOCKED_TIMEOUT 600000U 161 162 static void pm_pll_wait_lock(uint32_t pll_base) 163 { 164 int delay = PLL_LOCKED_TIMEOUT; 165 166 if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) 167 return; 168 169 while (delay-- >= 0) { 170 if ((mmio_read_32(pll_base + CRU_PLL_CON(6)) & CRU_PLLCON6_LOCK_STATUS) != 0) 171 break; 172 udelay(1); 173 } 174 175 if (delay <= 0) 176 ERROR("Can't wait pll(0x%x) lock\n", pll_base); 177 } 178 179 void qos_save(void) 180 { 181 uint32_t pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); 182 183 if ((pmu_pd_st & BIT(pmu_pd_nvm)) == 0) { 184 rockchip_reg_rgn_save(&qos_reg_rgns[qos_emmc], 1); 185 rockchip_reg_rgn_save(&qos_reg_rgns[qos_fspi0], 1); 186 } 187 188 if ((pmu_pd_st & BIT(pmu_pd_sd_gmac)) == 0) { 189 rockchip_reg_rgn_save(&qos_reg_rgns[qos_fspi1], 1); 190 rockchip_reg_rgn_save(&qos_reg_rgns[qos_gmac0], 1); 191 rockchip_reg_rgn_save(&qos_reg_rgns[qos_gmac1], 1); 192 rockchip_reg_rgn_save(&qos_reg_rgns[qos_sdio], 1); 193 rockchip_reg_rgn_save(&qos_reg_rgns[qos_sdmmc], 1); 194 rockchip_reg_rgn_save(&qos_reg_rgns[qos_flexbus], 1); 195 } 196 197 if ((pmu_pd_st & BIT(pmu_pd_php)) == 0) { 198 rockchip_reg_rgn_save(&qos_reg_rgns[qos_mmu0], 1); 199 rockchip_reg_rgn_save(&qos_reg_rgns[qos_mmu1], 1); 200 } 201 202 if ((pmu_pd_st & BIT(pmu_pd_vop)) == 0) { 203 rockchip_reg_rgn_save(&qos_reg_rgns[qos_vop_m0], 1); 204 rockchip_reg_rgn_save(&qos_reg_rgns[qos_vop_m1ro], 1); 205 } 206 207 if ((pmu_pd_st & BIT(pmu_pd_vo1)) == 0) 208 rockchip_reg_rgn_save(&qos_reg_rgns[qos_hdcp1], 1); 209 210 if ((pmu_pd_st & BIT(pmu_pd_vo0)) == 0) 211 rockchip_reg_rgn_save(&qos_reg_rgns[qos_hdcp0], 1); 212 213 if ((pmu_pd_st & BIT(pmu_pd_usb)) == 0) { 214 rockchip_reg_rgn_save(&qos_reg_rgns[qos_mmu2], 1); 215 rockchip_reg_rgn_save(&qos_reg_rgns[qos_ufshc], 1); 216 } 217 218 if ((pmu_pd_st & BIT(pmu_pd_vi)) == 0) { 219 rockchip_reg_rgn_save(&qos_reg_rgns[qos_isp_mro], 1); 220 rockchip_reg_rgn_save(&qos_reg_rgns[qos_isp_mwo], 1); 221 rockchip_reg_rgn_save(&qos_reg_rgns[qos_vicap_m0], 1); 222 rockchip_reg_rgn_save(&qos_reg_rgns[qos_vpss_mro], 1); 223 rockchip_reg_rgn_save(&qos_reg_rgns[qos_vpss_mwo], 1); 224 } 225 226 if ((pmu_pd_st & BIT(pmu_pd_vepu0)) == 0) 227 rockchip_reg_rgn_save(&qos_reg_rgns[qos_vepu0], 1); 228 229 if ((pmu_pd_st & BIT(pmu_pd_vepu1)) == 0) 230 rockchip_reg_rgn_save(&qos_reg_rgns[qos_vepu1], 1); 231 232 if ((pmu_pd_st & BIT(pmu_pd_vdec)) == 0) 233 rockchip_reg_rgn_save(&qos_reg_rgns[qos_rkvdec], 1); 234 235 if ((pmu_pd_st & BIT(pmu_pd_vpu)) == 0) { 236 rockchip_reg_rgn_save(&qos_reg_rgns[qos_ebc], 1); 237 rockchip_reg_rgn_save(&qos_reg_rgns[qos_rga0], 1); 238 rockchip_reg_rgn_save(&qos_reg_rgns[qos_rga1], 1); 239 rockchip_reg_rgn_save(&qos_reg_rgns[qos_jpeg], 1); 240 rockchip_reg_rgn_save(&qos_reg_rgns[qos_vdpp], 1); 241 } 242 243 if ((pmu_pd_st & BIT(pmu_pd_nputop)) == 0) { 244 rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_mcu], 1); 245 rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_nsp0], 1); 246 rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_nsp1], 1); 247 rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_m0ro], 1); 248 rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_m1ro], 1); 249 } 250 251 if ((pmu_pd_st & BIT(pmu_pd_npu0)) == 0) 252 rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_m0], 1); 253 254 if ((pmu_pd_st & BIT(pmu_pd_npu1)) == 0) 255 rockchip_reg_rgn_save(&qos_reg_rgns[qos_npu_m1], 1); 256 257 if ((pmu_pd_st & BIT(pmu_pd_gpu)) == 0) 258 rockchip_reg_rgn_save(&qos_reg_rgns[qos_gpu], 1); 259 } 260 261 void qos_restore(void) 262 { 263 uint32_t pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); 264 265 if ((pmu_pd_st & BIT(pmu_pd_nvm)) == 0) { 266 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_emmc], 1); 267 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_fspi0], 1); 268 } 269 270 if ((pmu_pd_st & BIT(pmu_pd_sd_gmac)) == 0) { 271 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_fspi1], 1); 272 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_gmac0], 1); 273 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_gmac1], 1); 274 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_sdio], 1); 275 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_sdmmc], 1); 276 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_flexbus], 1); 277 } 278 279 if ((pmu_pd_st & BIT(pmu_pd_php)) == 0) { 280 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_mmu0], 1); 281 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_mmu1], 1); 282 } 283 284 if ((pmu_pd_st & BIT(pmu_pd_vop)) == 0) { 285 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vop_m0], 1); 286 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vop_m1ro], 1); 287 } 288 289 if ((pmu_pd_st & BIT(pmu_pd_vo1)) == 0) 290 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_hdcp1], 1); 291 292 if ((pmu_pd_st & BIT(pmu_pd_vo0)) == 0) 293 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_hdcp0], 1); 294 295 if ((pmu_pd_st & BIT(pmu_pd_usb)) == 0) { 296 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_mmu2], 1); 297 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_ufshc], 1); 298 } 299 300 if ((pmu_pd_st & BIT(pmu_pd_vi)) == 0) { 301 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_isp_mro], 1); 302 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_isp_mwo], 1); 303 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vicap_m0], 1); 304 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vpss_mro], 1); 305 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vpss_mwo], 1); 306 } 307 308 if ((pmu_pd_st & BIT(pmu_pd_vepu0)) == 0) 309 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vepu0], 1); 310 311 if ((pmu_pd_st & BIT(pmu_pd_vepu1)) == 0) 312 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vepu1], 1); 313 314 if ((pmu_pd_st & BIT(pmu_pd_vdec)) == 0) 315 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_rkvdec], 1); 316 317 if ((pmu_pd_st & BIT(pmu_pd_vpu)) == 0) { 318 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_ebc], 1); 319 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_rga0], 1); 320 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_rga1], 1); 321 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_jpeg], 1); 322 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_vdpp], 1); 323 } 324 325 if ((pmu_pd_st & BIT(pmu_pd_nputop)) == 0) { 326 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_mcu], 1); 327 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_nsp0], 1); 328 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_nsp1], 1); 329 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_m0ro], 1); 330 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_m1ro], 1); 331 } 332 333 if ((pmu_pd_st & BIT(pmu_pd_npu0)) == 0) 334 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_m0], 1); 335 336 if ((pmu_pd_st & BIT(pmu_pd_npu1)) == 0) 337 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_npu_m1], 1); 338 339 if ((pmu_pd_st & BIT(pmu_pd_gpu)) == 0) 340 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_gpu], 1); 341 } 342 343 void pd_usb2phy_save(void) 344 { 345 rockchip_reg_rgn_save(pd_usb2phy_reg_rgns, ARRAY_SIZE(pd_usb2phy_reg_rgns)); 346 } 347 348 void pd_usb2phy_restore(void) 349 { 350 rockchip_reg_rgn_restore(pd_usb2phy_reg_rgns, ARRAY_SIZE(pd_usb2phy_reg_rgns)); 351 } 352 353 static uint32_t b_cru_mode, l_cru_mode; 354 static uint32_t bcore_need_restore; 355 356 void pd_bcore_save(void) 357 { 358 pvtplls_cpub_suspend(); 359 360 b_cru_mode = mmio_read_32(BIGCORE_CRU_BASE + 0x280); 361 rockchip_reg_rgn_save(pd_bcore_reg_rgns, ARRAY_SIZE(pd_bcore_reg_rgns)); 362 363 bcore_need_restore = 1; 364 } 365 366 void pd_bcore_restore(void) 367 { 368 if (bcore_need_restore == 0) 369 return; 370 371 /* slow mode */ 372 mmio_write_32(BIGCORE_CRU_BASE + 0x280, 0x00030000); 373 374 rockchip_reg_rgn_restore(pd_bcore_reg_rgns, ARRAY_SIZE(pd_bcore_reg_rgns)); 375 376 /* trigger lcore/bcore mem_cfg */ 377 mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1)); 378 udelay(1); 379 mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1)); 380 381 /* restore mode */ 382 mmio_write_32(BIGCORE_CRU_BASE + 0x280, WITH_16BITS_WMSK(b_cru_mode)); 383 384 pvtplls_cpub_resume(); 385 386 bcore_need_restore = 0; 387 } 388 389 void pd_core_save(void) 390 { 391 pvtplls_suspend(); 392 393 b_cru_mode = mmio_read_32(BIGCORE_CRU_BASE + 0x280); 394 l_cru_mode = mmio_read_32(LITTLE_CRU_BASE + 0x280); 395 396 rockchip_reg_rgn_save(&qos_reg_rgns[qos_cci_m0], 1); 397 rockchip_reg_rgn_save(&qos_reg_rgns[qos_cci_m1], 1); 398 rockchip_reg_rgn_save(&qos_reg_rgns[qos_cci_m2], 1); 399 rockchip_reg_rgn_save(&qos_reg_rgns[qos_dap_lite], 1); 400 401 rockchip_reg_rgn_save(pd_core_reg_rgns, ARRAY_SIZE(pd_core_reg_rgns)); 402 } 403 404 void pd_core_restore(void) 405 { 406 /* slow mode */ 407 mmio_write_32(BIGCORE_CRU_BASE + 0x280, 0x00030000); 408 mmio_write_32(LITTLE_CRU_BASE + 0x280, 0x00030000); 409 410 rockchip_reg_rgn_restore(pd_core_reg_rgns, ARRAY_SIZE(pd_core_reg_rgns)); 411 412 /* trigger lcore/bcore mem_cfg */ 413 mmio_write_32(LITCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1)); 414 mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(1, 0x1, 1)); 415 udelay(1); 416 mmio_write_32(LITCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1)); 417 mmio_write_32(BIGCORE_GRF_BASE + 0x38, BITS_WITH_WMASK(0, 0x1, 1)); 418 419 /* wait lock */ 420 pm_pll_wait_lock(CCI_CRU_BASE + 0x40); 421 422 /* restore mode */ 423 mmio_write_32(BIGCORE_CRU_BASE + 0x280, WITH_16BITS_WMSK(b_cru_mode)); 424 mmio_write_32(LITTLE_CRU_BASE + 0x280, WITH_16BITS_WMSK(l_cru_mode)); 425 426 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_cci_m0], 1); 427 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_cci_m1], 1); 428 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_cci_m2], 1); 429 rockchip_reg_rgn_restore(&qos_reg_rgns[qos_dap_lite], 1); 430 431 pvtplls_resume(); 432 } 433 434 void pd_php_save(void) 435 { 436 rockchip_reg_rgn_save(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns)); 437 } 438 439 void pd_php_restore(void) 440 { 441 rockchip_reg_rgn_restore(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns)); 442 } 443 444 void pm_reg_rgns_init(void) 445 { 446 rockchip_alloc_region_mem(qos_reg_rgns, ARRAY_SIZE(qos_reg_rgns)); 447 rockchip_alloc_region_mem(pd_bcore_reg_rgns, ARRAY_SIZE(pd_bcore_reg_rgns)); 448 rockchip_alloc_region_mem(pd_core_reg_rgns, ARRAY_SIZE(pd_core_reg_rgns)); 449 rockchip_alloc_region_mem(pd_php_reg_rgns, ARRAY_SIZE(pd_php_reg_rgns)); 450 rockchip_alloc_region_mem(pd_usb2phy_reg_rgns, ARRAY_SIZE(pd_usb2phy_reg_rgns)); 451 } 452