1*9fd9f1d0Sshengfei Xu /* 2*9fd9f1d0Sshengfei Xu * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3*9fd9f1d0Sshengfei Xu * 4*9fd9f1d0Sshengfei Xu * SPDX-License-Identifier: BSD-3-Clause 5*9fd9f1d0Sshengfei Xu */ 6*9fd9f1d0Sshengfei Xu 7*9fd9f1d0Sshengfei Xu #ifndef __PLAT_DEF_H__ 8*9fd9f1d0Sshengfei Xu #define __PLAT_DEF_H__ 9*9fd9f1d0Sshengfei Xu 10*9fd9f1d0Sshengfei Xu #define MAJOR_VERSION (1) 11*9fd9f1d0Sshengfei Xu #define MINOR_VERSION (0) 12*9fd9f1d0Sshengfei Xu 13*9fd9f1d0Sshengfei Xu #define SIZE_K(n) ((n) * 1024) 14*9fd9f1d0Sshengfei Xu 15*9fd9f1d0Sshengfei Xu /* Special value used to verify platform parameters from BL2 to BL3-1 */ 16*9fd9f1d0Sshengfei Xu #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 17*9fd9f1d0Sshengfei Xu 18*9fd9f1d0Sshengfei Xu #define GIC600_BASE 0xfd400000 19*9fd9f1d0Sshengfei Xu #define GIC600_SIZE SIZE_K(64) 20*9fd9f1d0Sshengfei Xu 21*9fd9f1d0Sshengfei Xu #define PMUSGRF_BASE 0xfdc00000 22*9fd9f1d0Sshengfei Xu #define SYSSGRF_BASE 0xfdc10000 23*9fd9f1d0Sshengfei Xu #define PMUGRF_BASE 0xfdc20000 24*9fd9f1d0Sshengfei Xu #define CPUGRF_BASE 0xfdc30000 25*9fd9f1d0Sshengfei Xu #define DDRGRF_BASE 0xfdc40000 26*9fd9f1d0Sshengfei Xu #define PIPEGRF_BASE 0xfdc50000 27*9fd9f1d0Sshengfei Xu #define GRF_BASE 0xfdc60000 28*9fd9f1d0Sshengfei Xu #define PIPEPHY_GRF0 0xfdc70000 29*9fd9f1d0Sshengfei Xu #define PIPEPHY_GRF1 0xfdc80000 30*9fd9f1d0Sshengfei Xu #define PIPEPHY_GRF2 0xfdc90000 31*9fd9f1d0Sshengfei Xu #define USBPHY_U3_GRF 0xfdca0000 32*9fd9f1d0Sshengfei Xu #define USB2PHY_U2_GRF 0xfdca8000 33*9fd9f1d0Sshengfei Xu #define EDPPHY_GRF 0xfdcb0000 34*9fd9f1d0Sshengfei Xu #define SYSSRAM_BASE 0xfdcc0000 35*9fd9f1d0Sshengfei Xu #define PCIE30PHY_GRF 0xfdcb8000 36*9fd9f1d0Sshengfei Xu #define USBGRF_BASE 0xfdcf0000 37*9fd9f1d0Sshengfei Xu 38*9fd9f1d0Sshengfei Xu #define PMUCRU_BASE 0xfdd00000 39*9fd9f1d0Sshengfei Xu #define SCRU_BASE 0xfdd10000 40*9fd9f1d0Sshengfei Xu #define SGRF_BASE 0xfdd18000 41*9fd9f1d0Sshengfei Xu #define STIME_BASE 0xfdd1c000 42*9fd9f1d0Sshengfei Xu #define CRU_BASE 0xfdd20000 43*9fd9f1d0Sshengfei Xu #define PMUSCRU_BASE 0xfdd30000 44*9fd9f1d0Sshengfei Xu #define I2C0_BASE 0xfdd40000 45*9fd9f1d0Sshengfei Xu 46*9fd9f1d0Sshengfei Xu #define UART0_BASE 0xfdd50000 47*9fd9f1d0Sshengfei Xu #define GPIO0_BASE 0xfdd60000 48*9fd9f1d0Sshengfei Xu #define PMUPVTM_BASE 0xfdd80000 49*9fd9f1d0Sshengfei Xu #define PMU_BASE 0xfdd90000 50*9fd9f1d0Sshengfei Xu #define PMUSRAM_BASE 0xfdcd0000 51*9fd9f1d0Sshengfei Xu #define PMUSRAM_SIZE SIZE_K(128) 52*9fd9f1d0Sshengfei Xu #define PMUSRAM_RSIZE SIZE_K(8) 53*9fd9f1d0Sshengfei Xu 54*9fd9f1d0Sshengfei Xu #define DDRSGRF_BASE 0xfe200000 55*9fd9f1d0Sshengfei Xu #define UART1_BASE 0xfe650000 56*9fd9f1d0Sshengfei Xu #define UART2_BASE 0xfe660000 57*9fd9f1d0Sshengfei Xu #define GPIO1_BASE 0xfe740000 58*9fd9f1d0Sshengfei Xu #define GPIO2_BASE 0xfe750000 59*9fd9f1d0Sshengfei Xu #define GPIO3_BASE 0xfe760000 60*9fd9f1d0Sshengfei Xu #define GPIO4_BASE 0xfe770000 61*9fd9f1d0Sshengfei Xu 62*9fd9f1d0Sshengfei Xu #define REMAP_BASE 0xffff0000 63*9fd9f1d0Sshengfei Xu #define REMAP_SIZE SIZE_K(64) 64*9fd9f1d0Sshengfei Xu /************************************************************************** 65*9fd9f1d0Sshengfei Xu * UART related constants 66*9fd9f1d0Sshengfei Xu **************************************************************************/ 67*9fd9f1d0Sshengfei Xu #define FPGA_UART_BASE UART2_BASE 68*9fd9f1d0Sshengfei Xu #define FPGA_BAUDRATE 1500000 69*9fd9f1d0Sshengfei Xu #define FPGA_UART_CLOCK 24000000 70*9fd9f1d0Sshengfei Xu 71*9fd9f1d0Sshengfei Xu /****************************************************************************** 72*9fd9f1d0Sshengfei Xu * System counter frequency related constants 73*9fd9f1d0Sshengfei Xu ******************************************************************************/ 74*9fd9f1d0Sshengfei Xu #define SYS_COUNTER_FREQ_IN_TICKS 24000000 75*9fd9f1d0Sshengfei Xu #define SYS_COUNTER_FREQ_IN_MHZ 24 76*9fd9f1d0Sshengfei Xu 77*9fd9f1d0Sshengfei Xu /****************************************************************************** 78*9fd9f1d0Sshengfei Xu * GIC-600 & interrupt handling related constants 79*9fd9f1d0Sshengfei Xu ******************************************************************************/ 80*9fd9f1d0Sshengfei Xu 81*9fd9f1d0Sshengfei Xu /* Base rk_platform compatible GIC memory map */ 82*9fd9f1d0Sshengfei Xu #define PLAT_GICD_BASE GIC600_BASE 83*9fd9f1d0Sshengfei Xu #define PLAT_GICC_BASE 0 84*9fd9f1d0Sshengfei Xu #define PLAT_GICR_BASE (GIC600_BASE + 0x60000) 85*9fd9f1d0Sshengfei Xu 86*9fd9f1d0Sshengfei Xu /****************************************************************************** 87*9fd9f1d0Sshengfei Xu * sgi, ppi 88*9fd9f1d0Sshengfei Xu ******************************************************************************/ 89*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_PHY_TIMER 29 90*9fd9f1d0Sshengfei Xu 91*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_SGI_0 8 92*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_SGI_1 9 93*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_SGI_2 10 94*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_SGI_3 11 95*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_SGI_4 12 96*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_SGI_5 13 97*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_SGI_6 14 98*9fd9f1d0Sshengfei Xu #define RK_IRQ_SEC_SGI_7 15 99*9fd9f1d0Sshengfei Xu 100*9fd9f1d0Sshengfei Xu #define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/ 101*9fd9f1d0Sshengfei Xu #define SHARE_MEM_PAGE_NUM 15 102*9fd9f1d0Sshengfei Xu #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 103*9fd9f1d0Sshengfei Xu 104*9fd9f1d0Sshengfei Xu #endif /* __PLAT_DEF_H__ */ 105